{"id":6244,"date":"2026-09-14T08:00:00","date_gmt":"2026-09-14T00:00:00","guid":{"rendered":"https:\/\/www.topfastpcb.com\/?p=6244"},"modified":"2026-08-05T18:11:45","modified_gmt":"2026-08-05T10:11:45","slug":"skew-compensation-fwe-pcb","status":"publish","type":"post","link":"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/","title":{"rendered":"Sk\u00e6vhedskompensation: H\u00e5ndtering af fiberv\u00e6vningseffekten (FWE) og l\u00e6ngdetilpasning til PCIe Gen 6"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_74 counter-hierarchy ez-toc-counter ez-toc-custom ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Indholdsfortegnelse<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/#Introduction_to_PCIe_Gen_6_Signal_Integrity_Challenges\" >Introduktion til udfordringerne ved signalintegritet i PCIe Gen 6<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/#Understanding_Skew_in_High-Speed_Differential_Pairs\" >Forst\u00e5else af sk\u00e6vhed i h\u00f8jhastighedsdifferentialpar<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/#In-Pair_Skew_Intra-Pair_Skew\" >Sk\u00e6vhed inden for parret (Intra-Pair Skew)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/#Factors_Contributing_to_Skew\" >Faktorer, der bidrager til sk\u00e6vhed<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/#The_Fiber_Weave_Effect_FWE_Explained\" >Fiber Weave-effekten (FWE) forklaret<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/#The_Microscopic_Dielectric_Imbalance\" >Den mikroskopiske dielektriske ubalance<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/#Mitigation_Strategies_for_FWE\" >Strategier til afb\u00f8dning af FWE<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/#Precision_Length_Matching_and_Phase_Compensation\" >Pr\u00e6cis l\u00e6ngdetilpasning og fasekompensation<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/#Phase_Compensation_at_the_Source\" >Fasekompensation ved kilden<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/#Corner_and_Bend_Management\" >H\u00e5ndtering af sving og kurver<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/#How_to_Implement_Skew_Compensation_for_PCIe_Gen_6_Step-by-Step_Guide\" >S\u00e5dan implementeres skew-kompensation for PCIe Gen 6 (trin-for-trin-vejledning)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-12\" href=\"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/#Advanced_Considerations_for_64_GTs_Channels\" >Avancerede overvejelser vedr\u00f8rende 64 GT\/s-kanaler<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-13\" href=\"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/#Via_Stub_Management\" >Via Stub Management<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-14\" href=\"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/#Surface_Roughness_Impact\" >Indvirkning af overfladens ruhed<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-15\" href=\"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/#Conclusion\" >Konklusion<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-16\" href=\"https:\/\/www.topfastpcb.com\/da\/blog\/skew-compensation-fwe-pcb\/#Frequently_Asked_Questions_FAQ\" >Ofte stillede sp\u00f8rgsm\u00e5l (FAQ)<\/a><\/li><\/ul><\/nav><\/div>\n<h2><span class=\"ez-toc-section\" id=\"Introduction_to_PCIe_Gen_6_Signal_Integrity_Challenges\"><\/span>Introduktion til udfordringerne ved signalintegritet i PCIe Gen 6<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Overgangen til Peripheral Component Interconnect Express (PCIe) generation 6 medf\u00f8rer hidtil usete udfordringer inden for design af h\u00f8jhastigheds-printkort (PCB). PCIe Gen 6, der k\u00f8rer med 64 GigaTransfers pr. sekund (GT\/s) og anvender Pulse Amplitude Modulation 4-level (PAM4)-signalering, stiller strenge krav til styring af signalintegriteten (SI). PAM4 koder to bits pr. symbol ved hj\u00e6lp af fire sp\u00e6ndingsniveauer, hvilket reducerer signal-st\u00f8j-forholdet (SNR) og \u00f8jeh\u00f8jden betydeligt sammenlignet med Non-Return-to-Zero (NRZ)-signalering, der blev anvendt i tidligere generationer.<\/p>\n<p>I dette milj\u00f8 med h\u00f8je frekvenser og sm\u00e5 margener kan selv picosekunder af faseforskydning mellem de positive (P) og negative (N) spor i et differentielt par f\u00e5 signalets \u00f8jediagram til at bryde fuldst\u00e6ndigt sammen. Denne faseforskydning, der ofte kaldes skew, medf\u00f8rer konvertering fra differentiel til f\u00e6llesmodus, \u00f8get elektromagnetisk interferens (EMI) og \u00f8del\u00e6ggende resonanser i inds\u00e6tningstabet. For at sikre robust linktr\u00e6ning og lave bitfejlfrekvenser (BER) skal PCB-ingeni\u00f8rer implementere strenge strategier til kompensation af skew med s\u00e6rligt fokus p\u00e5 at afb\u00f8de Fiber Weave-effekten (FWE) og udf\u00f8re n\u00f8jagtige protokoller for l\u00e6ngdetilpasning.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Understanding_Skew_in_High-Speed_Differential_Pairs\"><\/span>Forst\u00e5else af sk\u00e6vhed i h\u00f8jhastighedsdifferentialpar<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Skew i differentielle par forekommer i to prim\u00e6re former: skew inden for samme par og skew mellem par. For serielle forbindelser som PCIe Gen 6, hvor klokgenopretning er integreret i datastr\u00f8mmen, er skew inden for samme par den mest kritiske parameter, der skal kontrolleres.<\/p>\n<div style=\"text-align: center;\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-1.jpg\" alt=\"Sk\u00e6vhedskompensation\" width=\"600\" height=\"400\" class=\"aligncenter size-full wp-image-6417\" srcset=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-1.jpg 600w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-1-300x200.jpg 300w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-1-18x12.jpg 18w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/div>\n<h3><span class=\"ez-toc-section\" id=\"In-Pair_Skew_Intra-Pair_Skew\"><\/span>Sk\u00e6vhed inden for parret (Intra-Pair Skew)<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p>Sk\u00e6vhed i et par er forskellen i udbredelsesforsinkelse mellem den ikke-inverterende og den inverterende ledning i et enkelt differentielt par. Ideelt set b\u00f8r signaler, der sendes ud samtidigt, ankomme til modtageren pr\u00e6cis p\u00e5 samme tid og med en faseforskel p\u00e5 180 grader. N\u00e5r der opst\u00e5r sk\u00e6vhed, udligner signalerne ikke l\u00e6ngere hinanden perfekt. Denne fejljustering medf\u00f8rer, at en del af det differentielle signal omdannes til et common-mode-signal. Common-mode-signaler er yderst u\u00f8nskede, da de ikke drager fordel af st\u00f8jimmuniteten ved differentiel signalering, \u00f8ger EMI-emissionerne og skaber resonansdyk i profilen for differentielt inds\u00e6tningstab (SDD21). For PCIe Gen 6 ligger det samlede tilladte sk\u00e6vhedsbudget pr. par p\u00e5 tv\u00e6rs af hele kanalen typisk i st\u00f8rrelsesordenen nogle f\u00e5 pikosekunder.<\/p>\n<h3><span class=\"ez-toc-section\" id=\"Factors_Contributing_to_Skew\"><\/span>Faktorer, der bidrager til sk\u00e6vhed<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p>Flere faktorer bidrager til sk\u00e6vhed mellem par ved PCB-routing:<br \/>&#8211; <strong>Asymmetrisk routing:<\/strong> Uens sporl\u00e6ngder som f\u00f8lge af ukompenserede b\u00f8jninger, gennemf\u00f8ringer eller komponentudgange.<br \/>&#8211; <strong>Variationer i glasv\u00e6vning:<\/strong> De mikroskopiske uregelm\u00e6ssigheder i PCB-substratmaterialerne.<br \/>&#8211; <strong>Kobberoverfladens ruhed:<\/strong> Variationer i kobbersporets fysiske profil, selvom dette typisk er en sekund\u00e6r faktor for fasen.<br \/>&#8211; <strong>Afvigelser i stik og kabinetter:<\/strong> Pinout-geometrier, der i sagens natur medf\u00f8rer l\u00e6ngdeforskelle.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"The_Fiber_Weave_Effect_FWE_Explained\"><\/span>Fiber Weave-effekten (FWE) forklaret<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Ved fremstilling af h\u00f8jhastigheds-printkort best\u00e5r det dielektriske materiale typisk af en forst\u00e6rkningsmatrix af glasfiber, der er impr\u00e6gneret med en epoxyharpiks (f.eks. FR4-, Megtron- eller Rogers-materialer). Glasfibrene giver strukturel stivhed, mens harpiksen fungerer som bindemiddel. Disse to materialer har imidlertid v\u00e6sentligt forskellige dielektriske konstanter (Dk). Glasfibrene har generelt en h\u00f8jere Dk (omkring 6,0) sammenlignet med den omgivende harpiks (omkring 3,0).<\/p>\n<h3><span class=\"ez-toc-section\" id=\"The_Microscopic_Dielectric_Imbalance\"><\/span>Den mikroskopiske dielektriske ubalance<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p>N\u00e5r differentielle par f\u00f8res over dette heterogene substrat, bliver den fysiske placering af sporene i forhold til glasv\u00e6vet en afg\u00f8rende faktor. Hvis den positive ledning i et differentielt par f\u00f8res direkte over et t\u00e6t glasbundt, mens den negative ledning f\u00f8res over et harpiksrigt mellemrum (\u00bbvinduet\u00ab), vil de to signaler blive udsat for forskellige effektive dielektriske konstanter.<\/p>\n<div style=\"text-align: center;\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-2.jpg\" alt=\"Sk\u00e6vhedskompensation\" width=\"600\" height=\"400\" class=\"aligncenter size-full wp-image-6418\" srcset=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-2.jpg 600w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-2-300x200.jpg 300w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-2-18x12.jpg 18w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/div>\n<p>Da udbredelseshastigheden for et elektromagnetisk signal er omvendt proportional med kvadratroden af den dielektriske konstant, vil signalet, der bev\u00e6ger sig gennem glasbundtet med den h\u00f8jere Dk-v\u00e6rdi, udbrede sig langsommere end signalet, der bev\u00e6ger sig gennem harpiksspalten med den lavere Dk-v\u00e6rdi. Denne forskel i hastighed medf\u00f8rer en forskel i udbredelsesforsinkelsen, hvilket skaber en sk\u00e6vhed inden for parret, der er fuldst\u00e6ndig uafh\u00e6ngig af den fysiske sporl\u00e6ngde. Dette f\u00e6nomen kaldes Fiber Weave-effekten (FWE).<\/p>\n<p>Ved Nyquist-frekvenser p\u00e5 32 GHz for PCIe Gen 6 kan selv en minimal FWE-for\u00e5rsaget sk\u00e6vhed opbruge hele fejlbudgettet. Standardglasv\u00e6vninger som 106 eller 1080 har markante mellemrum mellem bundterne, hvilket g\u00f8r dem meget f\u00f8lsomme over for FWE.<\/p>\n<h3><span class=\"ez-toc-section\" id=\"Mitigation_Strategies_for_FWE\"><\/span>Strategier til afb\u00f8dning af FWE<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p>For at h\u00e5ndtere FWE i PCIe Gen 6-design skal PCB-ingeni\u00f8rer anvende en eller en kombination af f\u00f8lgende teknikker: <strong>F\u00e5 mere at vide om <a href=\"\/da\/blog\/bga-underfill-pcba\/\">BGA-underfill: Forbedring af PCBA-p\u00e5lideligheden over for mekaniske st\u00f8d og termisk belastning<\/a>.<\/strong><\/p>\n<ul>\n<li><strong>Mekanisk spredt glas:<\/strong> Der anvendes avancerede laminater med mekanisk spredte eller udfladede glasfibre (f.eks. v\u00e6vningstyperne 1078, 1086, 2116 og 3313). Disse v\u00e6vningstyper minimerer harpiksomr\u00e5derne og giver dermed en mere homogen Dk-profil for ledningerne.<\/li>\n<li><strong>Diagonal routing:<\/strong> F\u00f8ring af h\u00f8jhastighedsspor i en vinkel (typisk 10 til 15 grader) i forhold til den prim\u00e6re X-Y-akse i printkortets v\u00e6vning. Dette sikrer, at begge spor krydser skiftevis glasfiberbundter og harpiksmellemrum i lige stor grad, hvilket udj\u00e6vner Dk-variationerne over sporets l\u00e6ngde.<\/li>\n<li><strong>Zig-zag-rutef\u00f8ring:<\/strong> Hvis det ikke er muligt at f\u00f8re ledningerne diagonalt p\u00e5 grund af begr\u00e6nsninger i printkortets form eller t\u00e6thed, kan man opn\u00e5 en tilsvarende udj\u00e6vningseffekt ved at f\u00f8re ledningerne i et diskret zigzagm\u00f8nster.<\/li>\n<li><strong>Roteret illustration:<\/strong> PCB-producenten kan under fremstillingen dreje hele panelets design en bestemt vinkel i forhold til laminatpladen, hvilket effektivt simulerer diagonal fr\u00e6sning af vinkelrette spor.<\/li>\n<\/ul>\n<h2><span class=\"ez-toc-section\" id=\"Precision_Length_Matching_and_Phase_Compensation\"><\/span>Pr\u00e6cis l\u00e6ngdetilpasning og fasekompensation<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Selvom afb\u00f8dning af FWE stabiliserer udbredelseshastigheden, skal de fysiske sporl\u00e6ngder stadig tilpasses omhyggeligt for at eliminere geometrisk sk\u00e6vhed. For PCIe Gen 6 er en simpel l\u00e6ngdetilpasning ikke tilstr\u00e6kkelig; der skal opn\u00e5s en reel fasekompensation.<\/p>\n<h3><span class=\"ez-toc-section\" id=\"Phase_Compensation_at_the_Source\"><\/span>Fasekompensation ved kilden<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p>En grundl\u00e6ggende regel inden for h\u00f8jhastigheds-routing er, at l\u00e6ngdeforskelle skal udlignes pr\u00e6cis d\u00e9r, hvor de opst\u00e5r. Hvis der opst\u00e5r en l\u00e6ngdeforskel ved en BGA-udgang eller en stikben, skal udligningsslinglen (eller \u00bbtrombone\u00ab- eller \u00bbharmonika\u00ab-strukturen) placeres umiddelbart ved siden af denne uregelm\u00e6ssighed.<\/p>\n<p>Hvis en l\u00e6ngdeforskel f\u00e5r lov til at brede sig ned ad kanalen, f\u00f8r den korrigeres, vil omdannelsen fra differentiel til f\u00e6llesmodus allerede have fundet sted. F\u00e6llesmodussignalet vil bev\u00e6ge sig med en lidt anden hastighed end det differentielle signal p\u00e5 grund af mikrostrips og striplines\u2019 modaldispersionsegenskaber. Kompensering i den fjerne ende kan m\u00e5ske korrigere DC-l\u00e6ngden, men det vil ikke v\u00e6re muligt at justere AC-fasen p\u00e5 tv\u00e6rs af hele frekvensb\u00e5ndet. <strong>F\u00e5 mere at vide om <a href=\"\/da\/blog\/extreme-thermal-cycling-aerospace-pcb\/\">Ekstreme temperaturcykler: P\u00e5lidelighedstest og materialevalg til printkort til luftfartsindustrien<\/a>.<\/strong><\/p>\n<h3><span class=\"ez-toc-section\" id=\"Corner_and_Bend_Management\"><\/span>H\u00e5ndtering af sving og kurver<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p>N\u00e5r et differentiaalpar passerer et hj\u00f8rne, tilbagel\u00e6gger den ydre ledning naturligvis en l\u00e6ngere str\u00e6kning end den indre ledning. For PCIe Gen 6 skal disse b\u00f8jninger styres n\u00f8je. Designere af h\u00f8jhastighedskredsl\u00f8b anvender typisk afkoblede bump eller specialiserede fasetilpassede geometrier umiddelbart efter et kn\u00e6k for at udligne den elektriske l\u00e6ngde. Alternativt kan man ved at anvende t\u00e6t kobling og bl\u00f8de buer i stedet for skarpe 45-graders vinkler minimere diskontinuiteten i den differentielle impedans og dannelsen af lokal sk\u00e6vhed.<\/p>\n<h2><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation.jpg\" alt=\"Sk\u00e6vhedskompensation\" width=\"600\" height=\"400\" class=\"aligncenter size-full wp-image-6416\" srcset=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation.jpg 600w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-300x200.jpg 300w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-18x12.jpg 18w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/h2>\n<h2><span class=\"ez-toc-section\" id=\"How_to_Implement_Skew_Compensation_for_PCIe_Gen_6_Step-by-Step_Guide\"><\/span>S\u00e5dan implementeres skew-kompensation for PCIe Gen 6 (trin-for-trin-vejledning)<span class=\"ez-toc-section-end\"><\/span><\/h2><div class=\"schema-how-to wp-block-yoast-how-to-block\"><p class=\"schema-how-to-description\">F\u00f8lg disse tekniske retningslinjer.<\/p> <ol class=\"schema-how-to-steps\"><li class=\"schema-how-to-step\" id=\"how-to-step-1\"><strong class=\"schema-how-to-step-name\">V\u00e6lg det rette dielektriske materiale og glasv\u00e6v<\/strong> <p class=\"schema-how-to-step-text\">Start med at r\u00e5df\u00f8re dig med din PCB-producent og din leverand\u00f8r af laminat. Specificer materialer med ultralavt tab, der har en flad eller mekanisk udbredt glasv\u00e6vsarkitektur (f.eks. 2116 eller 3313). S\u00f8rg for, at materialets Dk- og Df-egenskaber er stabile p\u00e5 tv\u00e6rs af frekvensspektret op til mindst 40 GHz.<\/p> <\/li><li class=\"schema-how-to-step\" id=\"how-to-step-2\"><strong class=\"schema-how-to-step-name\">Fastl\u00e6g rutef\u00f8ringsstrategien for afb\u00f8dning af FWE<\/strong> <p class=\"schema-how-to-step-text\">Fastl\u00e6g, hvordan FWE skal h\u00e5ndteres, ud fra dit kortets formfaktor og produktionsm\u00e6ssige begr\u00e6nsninger. Hvis layoutet tillader det, skal du fastl\u00e6gge en global designregel, der foreskrev, at alle PCIe Gen 6-differentialpar skal f\u00f8res i en vinkel p\u00e5 10 til 15 grader i forhold til de ortogonale akser. Hvis ikke, skal du kr\u00e6ve zigzag-f\u00f8ring eller forhandle om panelrotation med producenten.<\/p> <\/li><li class=\"schema-how-to-step\" id=\"how-to-step-3\"><strong class=\"schema-how-to-step-name\">Indf\u00f8r strenge regler for l\u00e6ngdeoverensstemmelse inden for par<\/strong> <p class=\"schema-how-to-step-text\">Konfigurer dit EDA-v\u00e6rkt\u00f8js begr\u00e6nsningsmanager til at h\u00e5ndh\u00e6ve strenge regler for l\u00e6ngdeoverensstemmelse inden for par. Ved drift p\u00e5 64 GT\/s b\u00f8r den dynamiske fasetolerance inden for par begr\u00e6nses til under 1 pikosekund (hvilket svarer til ca. 5\u20136 mils afh\u00e6ngigt af Dk). Indstil dynamisk fasekontrol i stedet for statisk l\u00e6ngdekontrol for at sikre kontinuerlig justering.<\/p> <\/li><li class=\"schema-how-to-step\" id=\"how-to-step-4\"><strong class=\"schema-how-to-step-name\">Udf\u00f8r lokaliseret fasekompensation<\/strong> <p class=\"schema-how-to-step-text\">F\u00f8r differentiaalparrene omhyggeligt, og s\u00f8rg for, at eventuelle geometriske afvigelser for\u00e5rsaget af komponentpads, via-overgange eller b\u00f8jninger straks korrigeres. Brug t\u00e6tte, lokaliserede slingreforl\u00f8b. Undg\u00e5 store, svungne kompensationsstrukturer, der kan medf\u00f8re u\u00f8nsket kapacitiv eller induktiv kobling.<\/p> <\/li><li class=\"schema-how-to-step\" id=\"how-to-step-5\"><strong class=\"schema-how-to-step-name\">Validering ved hj\u00e6lp af 3D-elektromagnetisk simulering<\/strong> <p class=\"schema-how-to-step-text\">Inden layoutet f\u00e6rdigg\u00f8res, skal de kritiske PCIe Gen 6-kanaler udskilles ved hj\u00e6lp af en 3D-fuldb\u00f8lge-EM-l\u00f8ser. Analyser S-parametrene i blandet tilstand, med s\u00e6rligt fokus p\u00e5 det differentielle inds\u00e6tningstab (SDD21) og konverteringen fra differentiel til f\u00e6lles tilstand (SCD21). Se efter markante resonansfald i SDD21-profilen, da disse ofte indikerer ukompenseret faseforskydning. Iter\u00e9r layoutet p\u00e5 baggrund af feedback fra simuleringen, indtil kanalen opfylder PCIe Gen 6-overensstemmelsesmasken.<\/p> <\/li><\/ol><\/div><p>Implementering af en robust strategi til kompensation for sk\u00e6vhed kr\u00e6ver en systematisk tilgang, der str\u00e6kker sig fra skematisk udformning til fysisk layout og simulering. F\u00f8lg disse trin for at sikre overholdelse af PCIe Gen 6-specifikationerne.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Advanced_Considerations_for_64_GTs_Channels\"><\/span>Avancerede overvejelser vedr\u00f8rende 64 GT\/s-kanaler<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>I takt med at datahastighederne forts\u00e6tter med at stige, bliver definitionen af en \u00bbsporl\u00e6ngde\u00ab stadig mere kompleks. PCB-designv\u00e6rkt\u00f8jer skal ogs\u00e5 tage h\u00f8jde for overgangene p\u00e5 Z-aksen. L\u00e6ngden af viaer, is\u00e6r afstanden fra det \u00f8verste lag til de indre signallag, medf\u00f8rer lokale forsinkelser, som skal udlignes symmetrisk.<\/p>\n<h3><span class=\"ez-toc-section\" id=\"Via_Stub_Management\"><\/span>Via Stub Management<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p>I forbindelse med PCIe Gen 6 fungerer via-stubs som resonansantenner og skal kontrolleres n\u00f8je. Backdrilling (boring med kontrolleret dybde) eller anvendelse af blinde\/nedgravede vias er obligatorisk for at eliminere resonansstubber, der kan skabe dybe nulpunkter i kanalens inds\u00e6tningstabsprofil. N\u00e5r der kompenseres for sk\u00e6vhed i n\u00e6rheden af vias, skal man sikre, at kompensationsstrukturen tager h\u00f8jde for den elektriske l\u00e6ngde af selve via-cylinderen. <strong>F\u00e5 mere at vide om <a href=\"\/da\/blog\/embedded-pcb-components-iot\/\">Indbyggede komponenter: Miniaturisering af IoT-enheder med indbyggede PCB-komponenter<\/a>.<\/strong><\/p>\n<h3><span class=\"ez-toc-section\" id=\"Surface_Roughness_Impact\"><\/span>Indvirkning af overfladens ruhed<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p>Mens FWE bestemmer fasevariationen, har kobberoverfladens ruhed en afg\u00f8rende indflydelse p\u00e5 inds\u00e6tningstabet ved Nyquist-frekvenser p\u00e5 32 GHz. \u00bbSkin-effekten\u00ab tvinger h\u00f8jfrekvente str\u00f8mme til at bev\u00e6ge sig langs kobberbanens ydre overflade. Grovere kobberbehandlinger (som standard RTF) \u00f8ger den effektive banel\u00e6ngde, hvilket medf\u00f8rer overdreven d\u00e6mpning og fasedispersion. Angiv kobberfolier med lav profil (LP), meget lav profil (VLP) eller hyperlav profil (HVLP) for at bevare signalintegriteten og minimere uforudsigelige faseforskydninger for\u00e5rsaget af variationer i ruheden.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Conclusion\"><\/span>Konklusion<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Design af printkort til PCIe Gen 6 kr\u00e6ver et paradigmeskifte i ingeni\u00f8rernes tilgang til signalintegritet. Den enorme hastighed p\u00e5 64 GT\/s ved PAM4-signalering reducerer tolerancen over for eventuelle uregelm\u00e6ssigheder i kanalerne drastisk. H\u00e5ndtering af sk\u00e6vhed inden for et par handler ikke l\u00e6ngere blot om at tilpasse sporl\u00e6ngder p\u00e5 et 2D-plan; det kr\u00e6ver en helhedsorienteret tilgang, der tager h\u00f8jde for interkonnektens 3D-geometri, de dielektriske materialers mikroskopiske struktur og de elektromagnetiske b\u00f8lgers dynamiske adf\u00e6rd. Ved n\u00f8je at styre Fiber Weave-effekten, implementere lokaliseret fasekompensation og benytte avanceret EM-simulering kan ingeni\u00f8rer med succes implementere robuste og p\u00e5lidelige PCIe Gen 6-arkitekturer. <strong>F\u00e5 mere at vide om <a href=\"\/da\/blog\/return-path-optimization-si\/\">Optimering af returvejen: Udformning af stabile referenceplaner til signalintegritet ved h\u00f8je frekvenser<\/a>.<\/strong><\/p>\n<h2><span class=\"ez-toc-section\" id=\"Frequently_Asked_Questions_FAQ\"><\/span>Ofte stillede sp\u00f8rgsm\u00e5l (FAQ)<span class=\"ez-toc-section-end\"><\/span><\/h2><div class=\"schema-faq wp-block-yoast-faq-block\"><div class=\"schema-faq-section\" id=\"faq-question-1\"><strong class=\"schema-faq-question\">Hvad er den maksimalt tilladte sk\u00e6vhed mellem to ledninger i et differentielt par i PCIe Gen 6?<\/strong> <p class=\"schema-faq-answer\">Selvom det n\u00f8jagtige budget afh\u00e6nger af hele kanalens sammens\u00e6tning (siliciumpakker, stik, kabler), er den typiske tommelfingerregel for printkortdelen af en PCIe Gen 6-forbindelse at holde sk\u00e6vheden inden for et par under 1 til 2 pikosekunder (ca. 5 til 10 mil i sporl\u00e6ngde, afh\u00e6ngigt af materialet). Selv denne lille m\u00e6ngde kan forringe PAM4-\u00f8je-diagrammet betydeligt.<\/p> <\/div> <div class=\"schema-faq-section\" id=\"faq-question-2\"><strong class=\"schema-faq-question\">Hvorfor kan jeg ikke bare udligne l\u00e6ngdeforskellen i modtagerenden?<\/strong> <p class=\"schema-faq-answer\">Hvis der opst\u00e5r sk\u00e6vhed tidligt i kanalen (f.eks. ved udgangen fra senderenheden), skaber det en f\u00e6llesmodussignalkomponent. Da differentielle og f\u00e6llesmodussignaler udbreder sig med lidt forskellige hastigheder i standard-printkorttv\u00e6rsnit, \u00e6ndrer faseforholdet sig, efterh\u00e5nden som signalet bev\u00e6ger sig. Kompensation i den fjerne ende kan m\u00e5ske matche den fysiske l\u00e6ngde, men vil ikke kunne justere differentialfasen korrekt p\u00e5 tv\u00e6rs af alle frekvenser, hvilket f\u00f8rer til signalforringelse.<\/p> <\/div> <div class=\"schema-faq-section\" id=\"faq-question-3\"><strong class=\"schema-faq-question\">Er zigzag-rutef\u00f8ring eller diagonal rutef\u00f8ring bedst til at mindske \u00bbFiber Weave Effect\u00ab?<\/strong> <p class=\"schema-faq-answer\">Diagonal ledningsf\u00f8ring (ledningsf\u00f8ring uden for aksen) anses generelt for at v\u00e6re bedre og mere ensartet til at mindske FWE. Zigzag-ledningsf\u00f8ring kan undertiden medf\u00f8re mindre impedansafbrydelser ved vendepunkterne, is\u00e6r hvis zigzag-segmenterne er korte i forhold til signalets b\u00f8lgel\u00e6ngde. Hvis pladsforholdene eller kretskortets form imidlertid forhindrer diagonal ledningsf\u00f8ring eller rotation af panelet, er zigzag-ledningsf\u00f8ring et brugbart alternativ, n\u00e5r den simuleres korrekt.<\/p> <\/div> <div class=\"schema-faq-section\" id=\"faq-question-4\"><strong class=\"schema-faq-question\">Skal jeg bekymre mig om sk\u00e6vhed mellem par i PCIe Gen 6?<\/strong> <p class=\"schema-faq-answer\">PCIe-arkitekturen h\u00e5ndterer i sagens natur par-til-par-skew (lane-til-lane-skew) p\u00e5 protokol- og chipniveau gennem en proces kaldet \u00bblane deskewing\u00ab under link-tr\u00e6ning. Derfor har PCB-designere meget l\u00f8sere tolerancer for l\u00e6ngdeafstemning mellem par (ofte op til flere inches) sammenlignet med de ekstremt stramme krav, der stilles til sk\u00e6vhed inden for et par.<\/p> <\/div> <div class=\"schema-faq-section\" id=\"faq-question-5\"><strong class=\"schema-faq-question\">Hvordan g\u00f8r PAM4-signalering sk\u00e6vhedskompensationen mere afg\u00f8rende end i tidligere PCIe-generationer?<\/strong> <p class=\"schema-faq-answer\">PAM4 anvender fire sp\u00e6ndingsniveauer til at overf\u00f8re to bits pr. symbol, hvilket reducerer den vertikale \u00f8jeh\u00f8jde (signal-st\u00f8j-forholdet) med cirka en faktor tre sammenlignet med NRZ-signalering, som anvendes i PCIe Gen 5 og tidligere versioner. Med en betydeligt mindre margen for st\u00f8j og jitter har enhver forvr\u00e6ngning for\u00e5rsaget af faseforskydning en uforholdsm\u00e6ssigt stor indvirkning p\u00e5 bitfejlraten (BER) i et PAM4-system.<\/p> <\/div> <\/div>","protected":false},"excerpt":{"rendered":"<p>Introduction to PCIe Gen 6 Signal Integrity Challenges The transition to Peripheral Component Interconnect Express (PCIe) Generation 6 introduces unprecedented challenges in high-speed printed circuit board (PCB) design. Operating at 64 GigaTransfers per second (GT\/s) and utilizing Pulse Amplitude Modulation 4-level (PAM4) signaling, PCIe Gen 6 demands stringent signal integrity (SI) management. PAM4 encodes two [&hellip;]<\/p>","protected":false},"author":1,"featured_media":6419,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_yoast_wpseo_focuskw":"Skew Compensation","_yoast_wpseo_title":"Skew Compensation: Managing Fiber Weave Effect (FWE) and Length Matching for PCIe Gen 6","_yoast_wpseo_metadesc":"Explore advanced techniques for managing Fiber Weave Effect (FWE) and achieving precise length matching in PCIe Gen 6 PCB designs to meet strict skew compensation requirements.","footnotes":""},"categories":[108],"tags":[580,582,581,110,579,578],"class_list":["post-6244","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news","tag-fiber-weave-effect","tag-high-speed-design","tag-length-matching","tag-pcb-design","tag-pcie-gen-6","tag-skew-compensation"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v25.1 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ 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