{"id":3746,"date":"2025-08-02T15:40:56","date_gmt":"2025-08-02T07:40:56","guid":{"rendered":"https:\/\/www.topfastpcb.com\/?p=3746"},"modified":"2025-08-02T17:55:17","modified_gmt":"2025-08-02T09:55:17","slug":"the-role-of-high-speed-pcb-routing-design","status":"publish","type":"post","link":"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/","title":{"rendered":"Conception de circuits imprim\u00e9s \u00e0 grande vitesse"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_74 counter-hierarchy ez-toc-counter ez-toc-custom ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table des mati\u00e8res<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#The_Role_of_High-Speed_PCB_Routing_Design\" >Le r\u00f4le de la conception du routage des circuits imprim\u00e9s \u00e0 grande vitesse<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#1_Ensuring_Signal_Integrity\" >1. Garantir l'int\u00e9grit\u00e9 du signal<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#2_Electromagnetic_Compatibility\" >2. Compatibilit\u00e9 \u00e9lectromagn\u00e9tique<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#3_System_Reliability\" >3. Fiabilit\u00e9 du syst\u00e8me<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#Fundamentals_of_High-Speed_PCB_Design\" >Principes de base de la conception de circuits imprim\u00e9s \u00e0 grande vitesse<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#1_Key_Elements_of_Signal_Integrity_SI\" >1. \u00c9l\u00e9ments cl\u00e9s de l'int\u00e9grit\u00e9 des signaux (IS)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#2_Power_Integrity_PI_Basics\" >2. Principes de base de l'int\u00e9grit\u00e9 de l'alimentation (PI)<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#High-Speed_PCB_Stackup_Design\" >Conception d'empilage de circuits imprim\u00e9s \u00e0 grande vitesse<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#1_Multilayer_Board_Stackup_Structure\" >1. Structure d'empilage des cartes multicouches<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#2_Advanced_Application_of_20H_Rule\" >2. Application avanc\u00e9e de la r\u00e8gle 20H<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#High-Speed_Signal_Routing_Techniques\" >Techniques de routage des signaux \u00e0 grande vitesse<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-12\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#1_Differential_Signaling_Routing\" >1. Acheminement diff\u00e9rentiel des signaux<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-13\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#2_Special_Handling_of_Clock_Signals\" >2. Traitement sp\u00e9cial des signaux d'horloge<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-14\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#Power_Integrity_Optimization\" >Optimisation de l'int\u00e9grit\u00e9 de l'alimentation<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-15\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#1_Power_Distribution_Network_PDN_Design\" >1. Conception du r\u00e9seau de distribution d'\u00e9lectricit\u00e9 (PDN)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-16\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#2_Simultaneous_Switching_Noise_SSN_Suppression\" >2. Suppression du bruit de commutation simultan\u00e9e (SSN)<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-17\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#EMCEMI_Design\" >Conception CEM\/EMI<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-18\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#1_Electromagnetic_Compatibility_EMC_Design\" >1. Conception de la compatibilit\u00e9 \u00e9lectromagn\u00e9tique (CEM)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-19\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#2_Ground_System_Optimization\" >2. Optimisation du syst\u00e8me au sol<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-20\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#High-Speed_PCB_Design_Verification\" >V\u00e9rification \u00e0 grande vitesse de la conception des circuits imprim\u00e9s<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-21\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#1_Signal_Integrity_SI_Analysis\" >1. Analyse de l'int\u00e9grit\u00e9 du signal (SI)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-22\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#2_Power_Integrity_PI_Verification\" >2. V\u00e9rification de l'int\u00e9grit\u00e9 de l'alimentation (PI)<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-23\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#Manufacturing_Process\" >Processus de fabrication<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-24\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#1_Design_for_Manufacturing_DFM\" >1. Conception pour la fabrication (DFM)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-25\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#2_Material_Selection\" >2. S\u00e9lection des mat\u00e9riaux<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-26\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#Key_Considerations_for_High-Speed_PCB_Routing_Design\" >Consid\u00e9rations cl\u00e9s pour la conception du routage des circuits imprim\u00e9s \u00e0 grande vitesse<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-27\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#Impedance_Control_and_Transmission_Line_Selection\" >Contr\u00f4le de l'imp\u00e9dance et s\u00e9lection des lignes de transmission<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-28\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#Routing_Strategies_to_Reduce_Crosstalk\" >Strat\u00e9gies d'acheminement pour r\u00e9duire la diaphonie<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-29\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#Mitigating_Reflections_and_Optimizing_Signal_Integrity\" >Att\u00e9nuation des r\u00e9flexions et optimisation de l'int\u00e9grit\u00e9 du signal<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-30\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#Final_Design_and_Verification\" >Conception finale et v\u00e9rification<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-31\" href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/the-role-of-high-speed-pcb-routing-design\/#Related_Recommendations\" >Recommandations connexes<\/a><\/li><\/ul><\/nav><\/div>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"The_Role_of_High-Speed_PCB_Routing_Design\"><\/span>Le r\u00f4le de la conception du routage des circuits imprim\u00e9s \u00e0 grande vitesse<span class=\"ez-toc-section-end\"><\/span><\/h2><p>Un routage correct garantit l'int\u00e9grit\u00e9 des signaux, am\u00e9liore la compatibilit\u00e9 \u00e9lectromagn\u00e9tique (CEM) et la fiabilit\u00e9 du syst\u00e8me.<\/p><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"1_Ensuring_Signal_Integrity\"><\/span>1. Garantir l'int\u00e9grit\u00e9 du signal<span class=\"ez-toc-section-end\"><\/span><\/h3><p>Une strat\u00e9gie de routage bien con\u00e7ue peut minimiser la r\u00e9flexion et la diaphonie des signaux, garantissant une transmission stable des donn\u00e9es \u00e0 haut d\u00e9bit (telles que USB 3.0, HDMI, etc.) sur le circuit imprim\u00e9.<\/p><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"2_Electromagnetic_Compatibility\"><\/span>2. Compatibilit\u00e9 \u00e9lectromagn\u00e9tique<span class=\"ez-toc-section-end\"><\/span><\/h3><p>L'adoption d'un syst\u00e8me de grille raisonnable pour normaliser les canaux de routage permet de r\u00e9duire les conflits d'espacement entre les composants ; la signalisation diff\u00e9rentielle, les couches de blindage et les plans de masse de l'alimentation permettent de minimiser les interf\u00e9rences \u00e9lectromagn\u00e9tiques (EMI).<\/p><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"3_System_Reliability\"><\/span>3. Fiabilit\u00e9 du syst\u00e8me<span class=\"ez-toc-section-end\"><\/span><\/h3><p>En contr\u00f4lant la densit\u00e9 du routage et l'utilisation des ressources, les chemins redondants peuvent \u00eatre minimis\u00e9s et les co\u00fbts r\u00e9duits ; les vias aveugles et les vias enterr\u00e9s peuvent optimiser le routage \u00e0 haute densit\u00e9. La normalisation de la disposition des grilles permet d'\u00e9viter les risques de court-circuit.<\/p><div class=\"wp-block-image\"><figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"600\" height=\"402\" src=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/08\/High-speed-PCB.jpg\" alt=\"PCB \u00e0 grande vitesse\" class=\"wp-image-3748\" srcset=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/08\/High-speed-PCB.jpg 600w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/08\/High-speed-PCB-300x201.jpg 300w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/08\/High-speed-PCB-18x12.jpg 18w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/figure><\/div><h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Fundamentals_of_High-Speed_PCB_Design\"><\/span>Principes de base de la conception de circuits imprim\u00e9s \u00e0 grande vitesse<span class=\"ez-toc-section-end\"><\/span><\/h2><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"1_Key_Elements_of_Signal_Integrity_SI\"><\/span>1. \u00c9l\u00e9ments cl\u00e9s de l'int\u00e9grit\u00e9 des signaux (IS)<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Effets des lignes de transmission<\/strong>: Les signaux \u00e0 haute fr\u00e9quence n\u00e9cessitent la prise en compte de la th\u00e9orie des lignes de transmission pour contr\u00f4ler l'adaptation de l'imp\u00e9dance caract\u00e9ristique.<\/li>\n\n<li><strong>Suppression de la r\u00e9flexion<\/strong>: Utiliser des r\u00e9sistances de terminaison pour r\u00e9duire la r\u00e9flexion du signal<\/li>\n\n<li><strong>Contr\u00f4le de la diaphonie<\/strong>: Appliquer la r\u00e8gle des 3W pour minimiser la diaphonie proche (NEXT) et la diaphonie lointaine (FEXT).<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"2_Power_Integrity_PI_Basics\"><\/span>2. Principes de base de l'int\u00e9grit\u00e9 de l'alimentation (PI)<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>R\u00e9seau de distribution d'\u00e9lectricit\u00e9 (PDN)<\/strong>: Optimiser la conception du plan de masse<\/li>\n\n<li><strong>Condensateurs de d\u00e9couplage<\/strong>: Mettre en place des r\u00e9seaux de d\u00e9couplage avec des combinaisons \"10\u03bcF+0,1\u03bcF+0,01\u03bcF\".<\/li>\n\n<li><strong>Bruit de commutation simultan\u00e9 (SSN)<\/strong>: R\u00e9duire l'impact des sorties de commutation simultan\u00e9es (SSO) gr\u00e2ce \u00e0 une disposition appropri\u00e9e<\/li><\/ul><h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"High-Speed_PCB_Stackup_Design\"><\/span>Haute vitesse <a href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/8-layer-pcb-stackup\/\">Conception de l'empilement des circuits imprim\u00e9s<\/a><span class=\"ez-toc-section-end\"><\/span><\/h2><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"1_Multilayer_Board_Stackup_Structure\"><\/span>1. Structure d'empilage des cartes multicouches<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Empilage typique<\/strong>: Configuration recommand\u00e9e \u00e0 8 couches (top-Gnd-Sig-Pwr-Sig-Gnd-Sig-bottom)<\/li>\n\n<li><strong>Contr\u00f4le de l'imp\u00e9dance<\/strong>: Obtenir une imp\u00e9dance 50\u03a9 pour les applications simples et 100\u03a9 pour les applications diff\u00e9rentielles gr\u00e2ce \u00e0 la conception de l'empilage.<\/li>\n\n<li><strong>Mat\u00e9riaux di\u00e9lectriques<\/strong>: Choisir des mat\u00e9riaux pour cartes haute fr\u00e9quence \u00e0 faible constante di\u00e9lectrique (Dk) et \u00e0 faible facteur de dissipation (Df).<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"2_Advanced_Application_of_20H_Rule\"><\/span>2. Application avanc\u00e9e de la r\u00e8gle 20H<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Indentation du plan de puissance<\/strong>: Le plan d'alimentation doit \u00eatre en retrait de 20H par rapport au plan de masse.<\/li>\n\n<li><strong>Suppression des interf\u00e9rences \u00e9lectromagn\u00e9tiques<\/strong>: R\u00e9duit efficacement le rayonnement des bords de 30 \u00e0 40 dB<\/li>\n\n<li><strong>Appareils mobiles<\/strong>: Ajouter des anneaux de protection et des vias de couture<\/li><\/ul><h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"High-Speed_Signal_Routing_Techniques\"><\/span>Techniques de routage des signaux \u00e0 grande vitesse<span class=\"ez-toc-section-end\"><\/span><\/h2><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"1_Differential_Signaling_Routing\"><\/span>1. Acheminement diff\u00e9rentiel des signaux<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Adaptation de la longueur<\/strong>: Contr\u00f4le de l'adaptation de la longueur des paires diff\u00e9rentielles \u00e0 \u00b15mil<\/li>\n\n<li><strong>Correspondance des phases<\/strong>: Maintien de la diff\u00e9rence de phase entre les signaux positifs\/n\u00e9gatifs &lt;5ps<\/li>\n\n<li><strong>D\u00e9lai intra-paire<\/strong>: Contr\u00f4le strict du skew intra-paire<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"2_Special_Handling_of_Clock_Signals\"><\/span>2. Traitement sp\u00e9cial des signaux d'horloge<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Traces de garde<\/strong>: Placez des traces de protection de la masse de part et d'autre des lignes d'horloge.<\/li>\n\n<li><strong>Techniques de r\u00e9siliation<\/strong>: Utiliser la terminaison de la source ou la terminaison de la fin<\/li>\n\n<li><strong>Contr\u00f4le de la gigue<\/strong>: R\u00e9duire la gigue temporelle gr\u00e2ce \u00e0 des r\u00e9seaux de distribution d'horloge \u00e0 faible gigue<\/li><\/ul><div class=\"wp-block-image\"><figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"600\" height=\"402\" src=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/08\/High-speed-PCB-2.jpg\" alt=\"PCB \u00e0 grande vitesse\" class=\"wp-image-3749\" srcset=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/08\/High-speed-PCB-2.jpg 600w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/08\/High-speed-PCB-2-300x201.jpg 300w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/08\/High-speed-PCB-2-18x12.jpg 18w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/figure><\/div><h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Power_Integrity_Optimization\"><\/span>Optimisation de l'int\u00e9grit\u00e9 de l'alimentation<span class=\"ez-toc-section-end\"><\/span><\/h2><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"1_Power_Distribution_Network_PDN_Design\"><\/span>1. Conception du r\u00e9seau de distribution d'\u00e9lectricit\u00e9 (PDN)<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Imp\u00e9dance cible<\/strong>: Maintenir l'imp\u00e9dance du PDN en dessous de la valeur cible sur toutes les fr\u00e9quences<\/li>\n\n<li><strong>Capacit\u00e9 du plan<\/strong>: Utiliser la capacit\u00e9 native entre les plans de puissance et de masse<\/li>\n\n<li><strong>Couverture des fr\u00e9quences<\/strong>: Le r\u00e9seau de d\u00e9couplage doit couvrir la plage DC \u00e0 GHz.<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"2_Simultaneous_Switching_Noise_SSN_Suppression\"><\/span>2. Suppression du bruit de commutation simultan\u00e9e (SSN)<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Segmentation de la puissance<\/strong>: Segmenter correctement les diff\u00e9rents domaines de tension<\/li>\n\n<li><strong>Chemin de retour<\/strong>: Veiller \u00e0 ce que les signaux \u00e0 grande vitesse aient des voies de retour \u00e0 faible imp\u00e9dance<\/li>\n\n<li><strong>Via le placement<\/strong>: Nombre suffisant de vias de puissance pour r\u00e9duire l'inductance de la boucle<\/li><\/ul><h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"EMCEMI_Design\"><\/span>Conception CEM\/EMI<span class=\"ez-toc-section-end\"><\/span><\/h2><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"1_Electromagnetic_Compatibility_EMC_Design\"><\/span>1. Conception de la compatibilit\u00e9 \u00e9lectromagn\u00e9tique (CEM)<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Contr\u00f4le des rayonnements<\/strong>: R\u00e9duire les \u00e9missions rayonn\u00e9es gr\u00e2ce \u00e0 la r\u00e8gle 20H et aux traces de protection<\/li>\n\n<li><strong>Circuits sensibles<\/strong>: Mise en place d'un blindage pour les circuits sensibles aux radiofr\u00e9quences<\/li>\n\n<li><strong>Conception du filtre<\/strong>: Installer des filtres de type \u03c0 ou T aux interfaces E\/S<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"2_Ground_System_Optimization\"><\/span>2. Optimisation du syst\u00e8me au sol<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Mise \u00e0 la terre hybride<\/strong>: Mettre en \u0153uvre une strat\u00e9gie de mise \u00e0 la terre hybride pour les circuits num\u00e9riques\/analogiques<\/li>\n\n<li><strong>Contr\u00f4le de la segmentation<\/strong>: \u00c9viter le rebond du sol caus\u00e9 par une segmentation incorrecte du plan de sol<\/li>\n\n<li><strong>Mise \u00e0 la terre multipoint<\/strong>: Utiliser une mise \u00e0 la terre multipoint pour les circuits \u00e0 haute fr\u00e9quence<\/li><\/ul><h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"High-Speed_PCB_Design_Verification\"><\/span>V\u00e9rification \u00e0 grande vitesse de la conception des circuits imprim\u00e9s<span class=\"ez-toc-section-end\"><\/span><\/h2><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"1_Signal_Integrity_SI_Analysis\"><\/span>1. Analyse de l'int\u00e9grit\u00e9 du signal (SI)<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Analyse du domaine temporel<\/strong>: \u00c9valuer la qualit\u00e9 du signal \u00e0 l'aide de diagrammes oculaires<\/li>\n\n<li><strong>Analyse dans le domaine des fr\u00e9quences<\/strong>: Analyser les caract\u00e9ristiques de transmission \u00e0 l'aide de param\u00e8tres S<\/li>\n\n<li><strong>V\u00e9rification de la simulation<\/strong>: Effectuer des simulations avant et apr\u00e8s la mise en page avec HyperLynx ou ADS<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"2_Power_Integrity_PI_Verification\"><\/span>2. V\u00e9rification de l'int\u00e9grit\u00e9 de l'alimentation (PI)<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Test d'imp\u00e9dance<\/strong>: Effectuer des tests d'imp\u00e9dance PDN entre le VRM et la puce.<\/li>\n\n<li><strong>Mesure du bruit<\/strong>: Mesure de l'ondulation de puissance et du bruit<\/li>\n\n<li><strong>Analyse thermique<\/strong>: \u00c9valuer l'\u00e9l\u00e9vation de temp\u00e9rature des traces \u00e0 courant \u00e9lev\u00e9<\/li><\/ul><div class=\"wp-block-image\"><figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"600\" height=\"402\" src=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/08\/High-speed-PCB-1.jpg\" alt=\"PCB \u00e0 grande vitesse\" class=\"wp-image-3750\" srcset=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/08\/High-speed-PCB-1.jpg 600w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/08\/High-speed-PCB-1-300x201.jpg 300w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/08\/High-speed-PCB-1-18x12.jpg 18w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/figure><\/div><h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Manufacturing_Process\"><\/span><a href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/pcb-manufacturing-process-flow\/\">Processus de fabrication<\/a><span class=\"ez-toc-section-end\"><\/span><\/h2><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"1_Design_for_Manufacturing_DFM\"><\/span>1. Conception pour la fabrication (DFM)<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Contr\u00f4le de la largeur de la trace<\/strong>: Tenir compte des effets du facteur de gravure<\/li>\n\n<li><strong>Rapport d'aspect<\/strong>: Maintenir le rapport entre l'\u00e9paisseur du panneau et le diam\u00e8tre du trou &lt;8:1<\/li>\n\n<li><strong>Finition de la surface<\/strong>: Pr\u00e9f\u00e9rer les finitions de surface ENIG ou argent par immersion.<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"2_Material_Selection\"><\/span>2. S\u00e9lection des mat\u00e9riaux<span class=\"ez-toc-section-end\"><\/span><\/h3><p>En appliquant ces principes de conception de circuits imprim\u00e9s \u00e0 grande vitesse et ces techniques d'optimisation des mots-cl\u00e9s, l'int\u00e9grit\u00e9 des signaux, l'int\u00e9grit\u00e9 de l'alimentation et les performances CEM des circuits imprim\u00e9s \u00e0 grande vitesse peuvent \u00eatre am\u00e9lior\u00e9es de mani\u00e8re significative. Au cours du processus de conception, il convient d'accorder une attention particuli\u00e8re aux facteurs cl\u00e9s tels que le contr\u00f4le de l'imp\u00e9dance, la r\u00e9duction de la diaphonie et l'optimisation de l'int\u00e9grit\u00e9 de l'alimentation, tout en utilisant des m\u00e9thodes de simulation et de mesure \u00e0 des fins de v\u00e9rification.<\/p><h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Key_Considerations_for_High-Speed_PCB_Routing_Design\"><\/span>Consid\u00e9rations cl\u00e9s pour la conception du routage des circuits imprim\u00e9s \u00e0 grande vitesse<span class=\"ez-toc-section-end\"><\/span><\/h2><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Impedance_Control_and_Transmission_Line_Selection\"><\/span>Contr\u00f4le de l'imp\u00e9dance et s\u00e9lection des lignes de transmission<span class=\"ez-toc-section-end\"><\/span><\/h3><p>Le contr\u00f4le de l'imp\u00e9dance est essentiel pour <a href=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/04\/Rigid-PCB25-1-300x300.jpg\">PCB \u00e0 grande vitesse<\/a> conception. S\u00e9lectionnez la structure de ligne de transmission appropri\u00e9e (par exemple, microruban ou stripline) en fonction de la fr\u00e9quence du signal, de l'\u00e9paisseur de la carte et de la constante di\u00e9lectrique. Utilisez des outils de calcul d'imp\u00e9dance (tels que Polar SI9000 ou la calculatrice int\u00e9gr\u00e9e d'Altium Designer) pour d\u00e9terminer avec pr\u00e9cision l'imp\u00e9dance de la trace et vous assurer qu'elle r\u00e9pond aux exigences de la conception. Par exemple, les paires diff\u00e9rentielles requi\u00e8rent g\u00e9n\u00e9ralement une imp\u00e9dance de 90\u03a9 ou 100\u03a9, ce qui n\u00e9cessite un contr\u00f4le strict de la largeur et de l'espacement des pistes. \u00c9vitez les discontinuit\u00e9s d'imp\u00e9dance caus\u00e9es par des coudes \u00e0 angle droit, des vias, des branches ou des changements soudains de largeur de trace, car elles peuvent entra\u00eener des r\u00e9flexions de signal et une d\u00e9gradation de l'int\u00e9grit\u00e9.<\/p><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Routing_Strategies_to_Reduce_Crosstalk\"><\/span>Strat\u00e9gies d'acheminement pour r\u00e9duire la diaphonie<span class=\"ez-toc-section-end\"><\/span><\/h3><p>La diaphonie est une menace majeure pour l'int\u00e9grit\u00e9 des signaux \u00e0 grande vitesse. Pour minimiser son impact :<\/p><ul class=\"wp-block-list\"><li><strong>Augmenter l'espacement des traces<\/strong>: Suivez la r\u00e8gle des 3W (espacement des traces adjacentes \u2265 3\u00d7 la largeur de la trace) pour r\u00e9duire le couplage \u00e9lectromagn\u00e9tique.<\/li>\n\n<li><strong>Utiliser la signalisation diff\u00e9rentielle<\/strong>: Les paires diff\u00e9rentielles (par exemple, USB, PCIe, LVDS) suppriment efficacement le bruit en mode commun, mais n\u00e9cessitent une largeur et un espacement pr\u00e9cis de la trace pour l'adaptation de l'imp\u00e9dance, ainsi qu'une adaptation stricte de la longueur.<\/li>\n\n<li><strong>Ajouter des couches de blindage<\/strong>: Acheminez les plans de masse (GND) autour des signaux sensibles (par exemple, les lignes d'horloge, les signaux RF) afin d'isoler les interf\u00e9rences externes.<\/li>\n\n<li><strong>\u00c9viter les longues traces parall\u00e8les<\/strong>: Le routage parall\u00e8le augmente le couplage - optez plut\u00f4t pour des croisements orthogonaux ou un espacement plus important.<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Mitigating_Reflections_and_Optimizing_Signal_Integrity\"><\/span>Att\u00e9nuation des r\u00e9flexions et optimisation de l'int\u00e9grit\u00e9 du signal<span class=\"ez-toc-section-end\"><\/span><\/h3><p>Les r\u00e9flexions du signal peuvent provoquer des d\u00e9passements, des anneaux et d'autres probl\u00e8mes de stabilit\u00e9. Les m\u00e9thodes d'optimisation comprennent :<\/p><ul class=\"wp-block-list\"><li><strong>Contr\u00f4le de la longueur de la trace<\/strong>: Les signaux \u00e0 grande vitesse (par exemple, DDR, HDMI) n\u00e9cessitent une adaptation stricte de la longueur afin d'\u00e9viter les d\u00e9calages temporels dus aux d\u00e9lais de propagation.<\/li>\n\n<li><strong>Adaptation d'imp\u00e9dance avec des r\u00e9sistances de terminaison<\/strong>: Choisissez la m\u00e9thode de terminaison appropri\u00e9e (s\u00e9rie, parall\u00e8le ou terminaison Thevenin) en fonction des caract\u00e9ristiques de la ligne de transmission afin d'\u00e9liminer les r\u00e9flexions.<\/li>\n\n<li><strong>Optimisation des plans de puissance et de masse<\/strong>: Utilisez des couches de puissance \u00e0 faible imp\u00e9dance et des plans de masse solides, ainsi que des condensateurs de d\u00e9couplage strat\u00e9giquement plac\u00e9s (par exemple, des combinaisons de 0,1\u03bcF et 10\u03bcF), afin de r\u00e9duire le bruit de puissance.<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Final_Design_and_Verification\"><\/span>Conception finale et v\u00e9rification<span class=\"ez-toc-section-end\"><\/span><\/h3><p>Une fois le routage termin\u00e9, effectuez une v\u00e9rification des r\u00e8gles de conception (DRC) pour garantir la conformit\u00e9 avec les exigences de fabrication des circuits imprim\u00e9s. Utiliser des outils de simulation SI\/PI (Signal Integrity\/Power Integrity) (par exemple, HyperLynx ou ADS) pour valider les chemins de signaux critiques et identifier rapidement les probl\u00e8mes potentiels.<\/p><p>La mise en \u0153uvre de ces mesures permet d'am\u00e9liorer consid\u00e9rablement la qualit\u00e9 du signal dans les circuits imprim\u00e9s \u00e0 grande vitesse, ce qui garantit la stabilit\u00e9 et la fiabilit\u00e9 du syst\u00e8me.<\/p><h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Related_Recommendations\"><\/span>Recommandations connexes<span class=\"ez-toc-section-end\"><\/span><\/h2><p><a href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/high-frequency-pcb-design-and-layout-guide\/\">Guide de conception et de mise en page de circuits imprim\u00e9s \u00e0 haute fr\u00e9quence<\/a><\/p><p><a href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/high-density-interconnector-pcb\/\">Interconnecteur haute densit\u00e9 PCB<\/a><\/p><p><a href=\"https:\/\/www.topfastpcb.com\/fr\/blog\/pcb-layout-design\/\">Conception du circuit imprim\u00e9<\/a><\/p>","protected":false},"excerpt":{"rendered":"<p>Les principes fondamentaux et les techniques avanc\u00e9es de la conception de circuits imprim\u00e9s \u00e0 grande vitesse, y compris la gestion de l'int\u00e9grit\u00e9 des signaux (th\u00e9orie des lignes de transmission, contr\u00f4le de la r\u00e9flexion), l'optimisation de l'int\u00e9grit\u00e9 de l'alimentation (conception PDN, strat\u00e9gies de d\u00e9couplage) et les consid\u00e9rations de compatibilit\u00e9 \u00e9lectromagn\u00e9tique (CEM), permettent d'obtenir des performances optimales dans la conception de circuits imprim\u00e9s \u00e0 grande vitesse tout en relevant les d\u00e9fis courants du d\u00e9veloppement de produits \u00e9lectroniques modernes.<\/p>","protected":false},"author":1,"featured_media":3751,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[112],"tags":[335,334,111],"class_list":["post-3746","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-knowledge","tag-high-speed-pcb","tag-high-speed-pcb-design","tag-pcb"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v25.1 - 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