{"id":3681,"date":"2025-07-25T08:49:00","date_gmt":"2025-07-25T00:49:00","guid":{"rendered":"https:\/\/www.topfastpcb.com\/?p=3681"},"modified":"2025-07-24T11:37:10","modified_gmt":"2025-07-24T03:37:10","slug":"common-issues-in-improving-pcb-reliability","status":"publish","type":"post","link":"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/","title":{"rendered":"Problemas comuns na melhoria da fiabilidade das PCB"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_74 counter-hierarchy ez-toc-counter ez-toc-custom ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">\u00cdndice<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#How_to_Calculate_PCB_Impedance\" >Como calcular a imped\u00e2ncia da placa de circuito impresso?<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#1_Determine_PCB_Stackup_Geometry\" >1. Determinar o empilhamento e a geometria da placa de circuito impresso<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#2_Identify_Dielectric_Constant_Dk_or_%CE%B5%E1%B5%A3\" >2. Identificar a constante diel\u00e9ctrica (Dk ou \u03b5\u1d63)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#3_Choose_Impedance_Calculation_Method\" >3. Selecionar o m\u00e9todo de c\u00e1lculo da imped\u00e2ncia<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#4_Use_Impedance_Calculators_or_Tools\" >4. Utilizar calculadoras ou ferramentas de imped\u00e2ncia<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#5_Optimize_Design_Based_on_Results\" >5. Otimizar a conce\u00e7\u00e3o com base nos resultados<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#How_to_consider_signal_integrity_in_PCB_design\" >Como considerar a integridade do sinal na conce\u00e7\u00e3o de PCB?<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#1_Layout_Design\" >1. Conce\u00e7\u00e3o do layout<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#2_Impedance_Matching\" >2. Correspond\u00eancia de imped\u00e2ncia<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#3_Signal_Line_Routing\" >3. Tra\u00e7ado da linha de sinaliza\u00e7\u00e3o<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#4_Power_and_Grounding\" >4. Alimenta\u00e7\u00e3o e liga\u00e7\u00e3o \u00e0 terra<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-12\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#5_Simulation_Verification\" >5. Verifica\u00e7\u00e3o da simula\u00e7\u00e3o<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-13\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#How_to_Consider_Electromagnetic_Compatibility_EMC_in_PCB_Design\" >Como considerar a compatibilidade electromagn\u00e9tica (EMC) na conce\u00e7\u00e3o de PCB?<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-14\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#1_PCB_Layout_for_EMC\" >1. Disposi\u00e7\u00e3o da placa de circuito impresso para CEM<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-15\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#2_Grounding_Techniques\" >2. T\u00e9cnicas de liga\u00e7\u00e3o \u00e0 terra<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-16\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#3_Filtering_Suppression\" >3. Filtragem e supress\u00e3o<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-17\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#4_Shielding_Interface_Design\" >4. Prote\u00e7\u00e3o e conce\u00e7\u00e3o da interface<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-18\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#5_Simulation_Testing\" >5. Simula\u00e7\u00e3o e ensaios<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-19\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#How_to_Consider_Power_Integrity_PI_in_PCB_Design\" >Como considerar a integridade da pot\u00eancia (PI) na conce\u00e7\u00e3o de PCB?<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-20\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#1_Power_Trace_Layout\" >1. Tra\u00e7ado do tra\u00e7o de pot\u00eancia<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-21\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#2_Power_Filtering\" >2. Filtragem de energia<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-22\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#3_Power_and_Grounding\" >3. Alimenta\u00e7\u00e3o e liga\u00e7\u00e3o \u00e0 terra<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-23\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#4_Simulation_and_Validation\" >4. Simula\u00e7\u00e3o e valida\u00e7\u00e3o<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-24\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#How_to_Incorporate_Design_for_Testability_DFT_in_PCB_Design\" >Como incorporar o design para testabilidade (DFT) no design de PCB?<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-25\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#1_Test_Points_and_Interfaces\" >1. Pontos e interfaces de teste<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-26\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#2_Board_Labeling_Silkscreen\" >2. Etiquetagem do quadro (serigrafia)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-27\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#3_Programmable_Test_Techniques\" >3. T\u00e9cnicas de ensaio program\u00e1veis<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-28\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#4_Simulation_and_Validation-2\" >4. Simula\u00e7\u00e3o e valida\u00e7\u00e3o<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-29\" href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/common-issues-in-improving-pcb-reliability\/#Key_Design_Principles_Comparison\" >Princ\u00edpios fundamentais de conce\u00e7\u00e3o Compara\u00e7\u00e3o<\/a><\/li><\/ul><\/li><\/ul><\/nav><\/div>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_to_Calculate_PCB_Impedance\"><\/span>Como calcular a imped\u00e2ncia da placa de circuito impresso?<span class=\"ez-toc-section-end\"><\/span><\/h2><p>O c\u00e1lculo da imped\u00e2ncia da placa de circuito impresso garante a integridade do sinal, especialmente para circuitos de alta velocidade e RF.<\/p><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"1_Determine_PCB_Stackup_Geometry\"><\/span>1. Determinar o empilhamento e a geometria da placa de circuito impresso<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Contagem de camadas<\/strong>: Simples, duplo ou multicamadas.<\/li>\n\n<li><strong>Largura do tra\u00e7o (W)<\/strong> e <strong>espessura (T)<\/strong>: Cr\u00edtico para o controlo da imped\u00e2ncia.<\/li>\n\n<li><strong>Espessura diel\u00e9ctrica (H)<\/strong>: Dist\u00e2ncia entre a camada de sinal e o plano de refer\u00eancia (por exemplo, terra).<\/li>\n\n<li><strong>Peso de cobre<\/strong>: Tipicamente 0,5 oz (17,5 \u00b5m) a 2 oz (70 \u00b5m).<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"2_Identify_Dielectric_Constant_Dk_or_%CE%B5%E1%B5%A3\"><\/span>2. Identificar a constante diel\u00e9ctrica (Dk ou \u03b5\u1d63)<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>FR-4<\/strong>: ~4,3-4,8 (varia consoante a frequ\u00eancia).<\/li>\n\n<li><strong>Rogers RO4003C<\/strong>: ~3,38 (baixa perda para RF).<\/li>\n\n<li><strong>Poliimida<\/strong>: ~3,5 (PCBs flex\u00edveis).<\/li>\n\n<li><em>Nota<\/em>: Dk diminui ligeiramente a frequ\u00eancias mais elevadas.<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"3_Choose_Impedance_Calculation_Method\"><\/span>3. Selecionar o m\u00e9todo de c\u00e1lculo da imped\u00e2ncia<span class=\"ez-toc-section-end\"><\/span><\/h3><p><strong>Microstrip<\/strong> (tra\u00e7o da camada exterior sobre o plano de terra):<\/p><div class=\"wp-block-image\"><figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"526\" height=\"74\" src=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/image.png\" alt=\"\" class=\"wp-image-3682\" srcset=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/image.png 526w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/image-300x42.png 300w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/image-18x3.png 18w\" sizes=\"auto, (max-width: 526px) 100vw, 526px\" \/><\/figure><\/div><p><strong>Fita adesiva<\/strong> (camada interna entre dois planos de terra):<\/p><div class=\"wp-block-image\"><figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"319\" height=\"63\" src=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/image-1.png\" alt=\"\" class=\"wp-image-3683\" srcset=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/image-1.png 319w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/image-1-300x59.png 300w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/image-1-18x4.png 18w\" sizes=\"auto, (max-width: 319px) 100vw, 319px\" \/><\/figure><\/div><p><strong>Par Diferencial<\/strong>: Requer um espa\u00e7amento (S) entre os tra\u00e7os.<\/p><div class=\"wp-block-image\"><figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"304\" height=\"49\" src=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/image-3.png\" alt=\"\" class=\"wp-image-3685\" srcset=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/image-3.png 304w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/image-3-300x49.png 300w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/image-3-18x3.png 18w\" sizes=\"auto, (max-width: 304px) 100vw, 304px\" \/><\/figure><\/div><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"4_Use_Impedance_Calculators_or_Tools\"><\/span>4. Utilizar calculadoras ou ferramentas de imped\u00e2ncia<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Ferramentas online<\/strong>: Kit de ferramentas Saturn PCB, Calculadora EEWeb.<\/li>\n\n<li><strong>Software PCB<\/strong>: O Altium Designer, o KiCad ou o Cadence incluem calculadores de imped\u00e2ncia incorporados.<\/li>\n\n<li><strong>Simuladores EM<\/strong>: Ansys HFSS, CST (para projectos avan\u00e7ados).<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"5_Optimize_Design_Based_on_Results\"><\/span>5. Otimizar a conce\u00e7\u00e3o com base nos resultados<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li>Ajustar <strong>largura do tra\u00e7o<\/strong> (\u2191 largura \u2192 \u2193 imped\u00e2ncia).<\/li>\n\n<li>Modificar <strong>espessura diel\u00e9ctrica<\/strong> (\u2191 H \u2192 \u2191 imped\u00e2ncia).<\/li>\n\n<li>Ajustar <strong>espa\u00e7amento entre tra\u00e7os<\/strong> para pares diferenciais.<\/li>\n\n<li>Selecionar <strong>materiais<\/strong> com Dk adequado (por exemplo, Rogers para RF).<\/li><\/ul><p><strong>Exemplo de c\u00e1lculo (FR-4 Microstrip)<\/strong><br>Dado:<\/p><ul class=\"wp-block-list\"><li>Largura do tra\u00e7o (W) = 0,2 mm<\/li>\n\n<li>Espessura diel\u00e9ctrica (H) = 0,15 mm<\/li>\n\n<li>Espessura do cobre (T) = 0,035 mm<\/li>\n\n<li>\u03b5\u1d63 = 4,5<\/li><\/ul><p>Utilizando a f\u00f3rmula de microstrip:<\/p><div class=\"wp-block-image\"><figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"491\" height=\"75\" src=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/image-4.png\" alt=\"\" class=\"wp-image-3686\" srcset=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/image-4.png 491w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/image-4-300x46.png 300w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/image-4-18x3.png 18w\" sizes=\"auto, (max-width: 491px) 100vw, 491px\" \/><\/figure><\/div><p>Corresponde \u00e0 imped\u00e2ncia padr\u00e3o de 50\u03a9 para sinais de RF.<\/p><div class=\"wp-block-image\"><figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"600\" height=\"402\" src=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/06\/PCB-electroplating-1.jpg\" alt=\"Os ensaios PCT submetem os produtos a\" class=\"wp-image-3454\" srcset=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/06\/PCB-electroplating-1.jpg 600w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/06\/PCB-electroplating-1-300x201.jpg 300w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/06\/PCB-electroplating-1-18x12.jpg 18w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/figure><\/div><h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_to_consider_signal_integrity_in_PCB_design\"><\/span>Como considerar a integridade do sinal em <a href=\"https:\/\/www.topfastpcb.com\/pt\/blog\/what-is-a-pcb-design\/\">Conce\u00e7\u00e3o de PCB<\/a>?<span class=\"ez-toc-section-end\"><\/span><\/h2><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"1_Layout_Design\"><\/span>1. Conce\u00e7\u00e3o do layout<span class=\"ez-toc-section-end\"><\/span><\/h3><p>Na conce\u00e7\u00e3o da disposi\u00e7\u00e3o da placa de circuito impresso, \u00e9 importante ter em conta a disposi\u00e7\u00e3o das linhas de sinal, linhas de alimenta\u00e7\u00e3o e linhas de terra e evitar interfer\u00eancias causadas pelo cruzamento de linhas de sinal, linhas de alimenta\u00e7\u00e3o e linhas de terra. Al\u00e9m disso, \u00e9 essencial minimizar o comprimento das linhas de sinal para reduzir a diafonia e o atraso.<\/p><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"2_Impedance_Matching\"><\/span>2. Correspond\u00eancia de imped\u00e2ncia<span class=\"ez-toc-section-end\"><\/span><\/h3><p>Ao conceber linhas de sinal de alta velocidade, deve ser efectuada a correspond\u00eancia de imped\u00e2ncias para garantir que a imped\u00e2ncia das linhas de sinal corresponde \u00e0 imped\u00e2ncia da fonte de sinal e da carga, evitando assim a reflex\u00e3o do sinal e a diafonia.<\/p><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"3_Signal_Line_Routing\"><\/span>3. Tra\u00e7ado da linha de sinaliza\u00e7\u00e3o<span class=\"ez-toc-section-end\"><\/span><\/h3><p>No projeto de PCB, o encaminhamento das linhas de sinal tamb\u00e9m afecta a integridade do sinal e deve seguir determinadas regras. Por exemplo, as linhas de sinal diferencial devem manter um determinado espa\u00e7amento e ser encaminhadas em paralelo, enquanto as linhas de sinal de extremidade \u00fanica devem ser encaminhadas paralelamente \u00e0s linhas de terra e as curvas das linhas de sinal devem ser minimizadas.<\/p><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"4_Power_and_Grounding\"><\/span>4. Alimenta\u00e7\u00e3o e liga\u00e7\u00e3o \u00e0 terra<span class=\"ez-toc-section-end\"><\/span><\/h3><p>Na conce\u00e7\u00e3o da placa de circuito impresso, a conce\u00e7\u00e3o da alimenta\u00e7\u00e3o e da liga\u00e7\u00e3o \u00e0 terra tamb\u00e9m afecta a integridade do sinal. Deve ser utilizada uma alimenta\u00e7\u00e3o e liga\u00e7\u00e3o \u00e0 terra est\u00e1veis e a resist\u00eancia e indut\u00e2ncia da alimenta\u00e7\u00e3o e liga\u00e7\u00e3o \u00e0 terra devem ser minimizadas tanto quanto poss\u00edvel.<\/p><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"5_Simulation_Verification\"><\/span>5. Verifica\u00e7\u00e3o da simula\u00e7\u00e3o<span class=\"ez-toc-section-end\"><\/span><\/h3><p>Ap\u00f3s a conclus\u00e3o do design da PCB, \u00e9 necess\u00e1ria a verifica\u00e7\u00e3o da simula\u00e7\u00e3o para garantir que a integridade do sinal cumpre os requisitos. Atrav\u00e9s da simula\u00e7\u00e3o, podem ser detectados problemas como o atraso do sinal, a reflex\u00e3o e a diafonia, e o design da PCB pode ser optimizado.<\/p><div class=\"wp-block-image\"><figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"600\" height=\"402\" src=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/PCB-soldering-2.jpg\" alt=\"Os ensaios PCT submetem os produtos a\" class=\"wp-image-3528\" srcset=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/PCB-soldering-2.jpg 600w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/PCB-soldering-2-300x201.jpg 300w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/07\/PCB-soldering-2-18x12.jpg 18w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/figure><\/div><h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_to_Consider_Electromagnetic_Compatibility_EMC_in_PCB_Design\"><\/span>Como considerar a compatibilidade electromagn\u00e9tica (EMC) na conce\u00e7\u00e3o de PCB?<span class=\"ez-toc-section-end\"><\/span><\/h2><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"1_PCB_Layout_for_EMC\"><\/span>1. Disposi\u00e7\u00e3o da placa de circuito impresso para CEM<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Minimizar o roteamento paralelo<\/strong>: Evite longos percursos paralelos entre os tra\u00e7os de sinal e de alimenta\u00e7\u00e3o\/terra para reduzir a diafonia e o acoplamento eletromagn\u00e9tico.<\/li>\n\n<li><strong>Isolamento de sinais cr\u00edticos<\/strong>: Separar sinais anal\u00f3gicos sens\u00edveis e de alta velocidade (por exemplo, rel\u00f3gios, RF) de circuitos ruidosos (por exemplo, fontes de alimenta\u00e7\u00e3o comutadas).<\/li>\n\n<li><strong>Estrat\u00e9gia de empilhamento de camadas<\/strong>:<\/li>\n\n<li>Utilizar planos de terra s\u00f3lidos adjacentes \u00e0s camadas de sinal para fornecer blindagem.<\/li>\n\n<li>Encaminhar sinais de alta velocidade em camadas interiores entre planos de terra para conten\u00e7\u00e3o.<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"2_Grounding_Techniques\"><\/span>2. T\u00e9cnicas de liga\u00e7\u00e3o \u00e0 terra<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Placas de terra de baixa imped\u00e2ncia<\/strong>: Utilize planos de terra ininterruptos para minimizar os circuitos de terra e reduzir as emiss\u00f5es por radia\u00e7\u00e3o.<\/li>\n\n<li><strong>Dividir os terrenos com cuidado<\/strong>: Separe as terras anal\u00f3gicas\/digitais apenas quando necess\u00e1rio, com um \u00fanico ponto de liga\u00e7\u00e3o (por exemplo, cord\u00e3o de ferrite ou resist\u00eancia de 0\u03a9).<\/li>\n\n<li><strong>Via Stitching<\/strong>: Colocar v\u00e1rias vias de terra \u00e0 volta dos tra\u00e7os de alta frequ\u00eancia ou dos bordos da placa para suprimir as resson\u00e2ncias da cavidade.<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"3_Filtering_Suppression\"><\/span>3. Filtragem e supress\u00e3o<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Contas de ferrite<\/strong>: Adicionar \u00e0s linhas de alimenta\u00e7\u00e3o\/IO para bloquear o ru\u00eddo de alta frequ\u00eancia.<\/li>\n\n<li><strong>Condensadores de desacoplamento<\/strong>: Colocar perto dos pinos de alimenta\u00e7\u00e3o do CI (por exemplo, 0,1\u03bcF + 1\u03bcF) para filtrar o ru\u00eddo de alta e m\u00e9dia frequ\u00eancia.<\/li>\n\n<li><strong>Bobinas de modo comum<\/strong>: Utilizar em pares diferenciais (por exemplo, USB, Ethernet) para suprimir a radia\u00e7\u00e3o de modo comum.<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"4_Shielding_Interface_Design\"><\/span>4. Prote\u00e7\u00e3o e conce\u00e7\u00e3o da interface<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Blindagem de cabos<\/strong>: Utilize conectores blindados (por exemplo, USB, HDMI) com liga\u00e7\u00e3o \u00e0 terra de 360\u00b0 para o chassis.<\/li>\n\n<li><strong>Blindagem ao n\u00edvel da placa<\/strong>: Adicionar latas de metal ou revestimentos condutores sobre circuitos de RF sens\u00edveis.<\/li>\n\n<li><strong>Prote\u00e7\u00e3o dos bordos<\/strong>: Encaminhar os tra\u00e7os sens\u00edveis para longe dos bordos da placa; utilizar tra\u00e7os de prote\u00e7\u00e3o ou cobre ligado \u00e0 terra \u00e0 sua volta.<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"5_Simulation_Testing\"><\/span>5. Simula\u00e7\u00e3o e ensaios<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>An\u00e1lise Pr\u00e9-Layout<\/strong>: Utilizar ferramentas como ANSYS HFSS ou CST para modelar os pontos cr\u00edticos de radia\u00e7\u00e3o.<\/li>\n\n<li><strong>Verifica\u00e7\u00e3o p\u00f3s-layout<\/strong>:<\/li>\n\n<li>Efetuar an\u00e1lises de campo pr\u00f3ximo para identificar fontes de emiss\u00e3o.<\/li>\n\n<li>Efetuar testes de conformidade (por exemplo, FCC, CE) para emiss\u00f5es por radia\u00e7\u00e3o\/condu\u00e7\u00e3o.<\/li>\n\n<li><strong>Itera\u00e7\u00e3o do projeto<\/strong>: Otimizar com base nos resultados dos testes (por exemplo, adicionar resist\u00eancias de termina\u00e7\u00e3o ou ajustar o espa\u00e7amento dos tra\u00e7os).<\/li><\/ul><p><strong>Exemplos de correc\u00e7\u00f5es<\/strong>:<\/p><ul class=\"wp-block-list\"><li>Um rel\u00f3gio de 100MHz irradia excessivamente: Adicionar resist\u00eancias de termina\u00e7\u00e3o em s\u00e9rie ou encaminhar entre planos de terra.<\/li>\n\n<li>Ru\u00eddo da fonte de alimenta\u00e7\u00e3o comutada: Implementar filtros \u03c0 (LC) na entrada\/sa\u00edda.<\/li><\/ul><p>Ao integrar estas pr\u00e1ticas, os PCBs podem cumprir as normas EMC (por exemplo, IEC 61000), minimizando as dispendiosas reformula\u00e7\u00f5es. Crie sempre um prot\u00f3tipo e teste com anteced\u00eancia!<\/p><div class=\"wp-block-image\"><figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"600\" height=\"402\" src=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/06\/pcba-2.jpg\" alt=\"Os ensaios PCT submetem os produtos a\" class=\"wp-image-3233\" srcset=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/06\/pcba-2.jpg 600w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/06\/pcba-2-300x201.jpg 300w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2025\/06\/pcba-2-18x12.jpg 18w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/figure><\/div><h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_to_Consider_Power_Integrity_PI_in_PCB_Design\"><\/span>Como considerar a integridade da pot\u00eancia (PI) na conce\u00e7\u00e3o de PCB?<span class=\"ez-toc-section-end\"><\/span><\/h2><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"1_Power_Trace_Layout\"><\/span>1. Tra\u00e7ado do tra\u00e7o de pot\u00eancia<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Tra\u00e7os curtos e largos<\/strong>: Minimizar a resist\u00eancia (R) e a indut\u00e2ncia parasita (L) para reduzir a queda de tens\u00e3o e o ru\u00eddo.<\/li>\n\n<li><strong>Evitar roteamento paralelo com tra\u00e7os de sinal<\/strong>: Impedir que o ru\u00eddo de pot\u00eancia seja acoplado a sinais sens\u00edveis (por exemplo, rel\u00f3gios, circuitos anal\u00f3gicos).<\/li>\n\n<li><strong>Estrat\u00e9gia de camadas<\/strong>:<\/li>\n\n<li>Em placas multicamadas, dedicar camadas inteiras aos planos de alimenta\u00e7\u00e3o e de terra.<\/li>\n\n<li>As barras de alimenta\u00e7\u00e3o cr\u00edticas (por exemplo, a tens\u00e3o do n\u00facleo da CPU) devem ter planos de alimenta\u00e7\u00e3o dedicados.<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"2_Power_Filtering\"><\/span>2. Filtragem de energia<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Condensadores de desacoplamento<\/strong>:<\/li>\n\n<li>Condensadores electrol\u00edticos a granel (10-100\u03bcF) nas entradas de alimenta\u00e7\u00e3o para estabilizar a tens\u00e3o.<\/li>\n\n<li>Pequenos condensadores de cer\u00e2mica (0,1 \u03bcF) perto dos pinos do CI para filtrar o ru\u00eddo de alta frequ\u00eancia.<\/li>\n\n<li><strong>Filtros LC<\/strong>:<\/li>\n\n<li>Adicionar filtros \u03c0 (condensador + indutor) para m\u00f3dulos sens\u00edveis ao ru\u00eddo (por exemplo, PLLs).<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"3_Power_and_Grounding\"><\/span>3. Alimenta\u00e7\u00e3o e liga\u00e7\u00e3o \u00e0 terra<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Caminhos de retorno de baixa imped\u00e2ncia<\/strong>:<\/li>\n\n<li>Utilizar planos de terra s\u00f3lidos; evitar divis\u00f5es que provoquem descontinuidades de imped\u00e2ncia.<\/li>\n\n<li>Vias m\u00faltiplas para ligar os planos de alimenta\u00e7\u00e3o\/terra (reduz a indut\u00e2ncia da via).<\/li>\n\n<li><strong>Liga\u00e7\u00e3o \u00e0 terra em estrela<\/strong>:<\/li>\n\n<li>Circuitos de alta pot\u00eancia e sens\u00edveis separados, com liga\u00e7\u00e3o \u00e0 terra num \u00fanico ponto.<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"4_Simulation_and_Validation\"><\/span>4. Simula\u00e7\u00e3o e valida\u00e7\u00e3o<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>An\u00e1lise PDN (Power Delivery Network)<\/strong>:<\/li>\n\n<li>Imped\u00e2ncia do alvo: ( Z_{\\text{target}} = \\frac{\\Delta V}{\\Delta I} ).<\/li>\n\n<li>Ferramentas: ANSYS SIwave, Cadence Sigrity.<\/li>\n\n<li><strong>Teste de ondula\u00e7\u00e3o e ru\u00eddo<\/strong>:<\/li>\n\n<li>Verificar os n\u00edveis de ru\u00eddo de pot\u00eancia com oscilosc\u00f3pios ou simula\u00e7\u00f5es.<\/li><\/ul><h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_to_Incorporate_Design_for_Testability_DFT_in_PCB_Design\"><\/span>Como incorporar o design para testabilidade (DFT) no design de PCB?<span class=\"ez-toc-section-end\"><\/span><\/h2><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"1_Test_Points_and_Interfaces\"><\/span>1. Pontos e interfaces de teste<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Pontos de teste de sinais cr\u00edticos<\/strong>:<\/li>\n\n<li>Fornecer vias ou almofadas (di\u00e2metro \u22651mm, espa\u00e7amento \u22652,54mm) para acesso \u00e0 sonda.<\/li>\n\n<li>Identifique os pontos de teste (por exemplo, TP1, TP2).<\/li>\n\n<li><strong>Interfaces padr\u00e3o<\/strong>:<\/li>\n\n<li>Colocar as interfaces JTAG, UART ou SWD perto dos bordos da placa.<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"2_Board_Labeling_Silkscreen\"><\/span>2. Etiquetagem do quadro (serigrafia)<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Marca\u00e7\u00f5es de componentes<\/strong>:<\/li>\n\n<li>Identifique os designadores de refer\u00eancia (por exemplo, R1, C2), a polaridade (+\/-) e o Pino 1.<\/li>\n\n<li>Utilizar serigrafia de alto contraste (branco\/preto).<\/li>\n\n<li><strong>Zonas funcionais<\/strong>:<\/li>\n\n<li>Delinear \u00e1reas (por exemplo, \"Sec\u00e7\u00e3o de Energia\") para facilitar a identifica\u00e7\u00e3o.<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"3_Programmable_Test_Techniques\"><\/span>3. T\u00e9cnicas de ensaio program\u00e1veis<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Varrimento de fronteira (JTAG)<\/strong>:<\/li>\n\n<li>Os CIs compat\u00edveis com IEEE 1149.1 (por exemplo, FPGAs, MCUs) permitem o teste de interconex\u00e3o.<\/li>\n\n<li><strong>Equipamento de teste automatizado (ATE)<\/strong>:<\/li>\n\n<li>Interfaces de fixa\u00e7\u00e3o de teste de reserva (por exemplo, pinos de pogo).<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"4_Simulation_and_Validation-2\"><\/span>4. Simula\u00e7\u00e3o e valida\u00e7\u00e3o<span class=\"ez-toc-section-end\"><\/span><\/h3><ul class=\"wp-block-list\"><li><strong>Verifica\u00e7\u00f5es de regras DFT<\/strong>:<\/li>\n\n<li>Assegurar a cobertura dos pontos de ensaio (por exemplo, &gt;90% de redes acess\u00edveis).<\/li>\n\n<li><strong>An\u00e1lise do modo de falha<\/strong>:<\/li>\n\n<li>Validar os circuitos de teste atrav\u00e9s de simula\u00e7\u00f5es SPICE.<\/li><\/ul><h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Key_Design_Principles_Comparison\"><\/span>Princ\u00edpios fundamentais de conce\u00e7\u00e3o Compara\u00e7\u00e3o<span class=\"ez-toc-section-end\"><\/span><\/h3><figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><thead><tr><th><strong>Integridade da energia (PI)<\/strong><\/th><th><strong>Conce\u00e7\u00e3o para Testabilidade (DFT)<\/strong><\/th><\/tr><\/thead><tbody><tr><td>Distribui\u00e7\u00e3o de energia de baixa imped\u00e2ncia<\/td><td>Acessibilidade do ponto de ensaio f\u00edsico<\/td><\/tr><tr><td>Otimiza\u00e7\u00e3o do condensador de desacoplamento<\/td><td>Suporte para varrimento JTAG\/limite<\/td><\/tr><tr><td>Minimizar o acoplamento pot\u00eancia-sinal<\/td><td>Etiquetagem clara dos componentes\/interface<\/td><\/tr><tr><td>Simula\u00e7\u00e3o PDN e an\u00e1lise de ondula\u00e7\u00e3o<\/td><td>Design compat\u00edvel com ATE<\/td><\/tr><\/tbody><\/table><\/figure><p><strong>Exemplos<\/strong>:<\/p><ul class=\"wp-block-list\"><li><strong>Otimiza\u00e7\u00e3o PI<\/strong>: Planos de alimenta\u00e7\u00e3o de mem\u00f3ria DDR4 com m\u00faltiplos tamp\u00f5es 0805 0.1\u03bcF (imped\u00e2ncia alvo \u22640.1\u03a9).<\/li>\n\n<li><strong>Implementa\u00e7\u00e3o de DFT<\/strong>: Placa de controlo industrial com 20 pontos de teste para testes automatizados com sondas voadoras.<\/li><\/ul><p>Ao abordar sistematicamente a PI e a DFT, os projectistas podem melhorar o desempenho energ\u00e9tico, a efici\u00eancia dos testes e a fiabilidade da produ\u00e7\u00e3o.<\/p><p><\/p>","protected":false},"excerpt":{"rendered":"<p>Como calcular a imped\u00e2ncia de PCB? O c\u00e1lculo da imped\u00e2ncia da placa de circuito impresso garante a integridade do sinal, especialmente para circuitos de alta velocidade e RF. 1. Determine o empilhamento e a geometria do PCB 2. Identifique a constante diel\u00e9trica (Dk ou \u03b5\u1d63) 3. Escolha o m\u00e9todo de c\u00e1lculo de imped\u00e2ncia Microstrip (tra\u00e7o da camada externa sobre o plano de aterramento): Stripline (camada interna entre dois planos de terra): Par Diferencial: Requer espa\u00e7amento (S) entre [...]<\/p>","protected":false},"author":1,"featured_media":3514,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[112],"tags":[111,330],"class_list":["post-3681","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-knowledge","tag-pcb","tag-pcb-reliability"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v25.1 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Common Issues in Improving PCB Reliability - Topfastpcb<\/title>\n<meta name=\"description\" content=\"Learn key strategies to improve PCB reliability, including impedance calculation, signal integrity, EMC, power integrity, and DFT. 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