{"id":6244,"date":"2026-09-14T08:00:00","date_gmt":"2026-09-14T00:00:00","guid":{"rendered":"https:\/\/www.topfastpcb.com\/?p=6244"},"modified":"2026-08-05T18:11:45","modified_gmt":"2026-08-05T10:11:45","slug":"skew-compensation-fwe-pcb","status":"publish","type":"post","link":"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/","title":{"rendered":"Skew-kompensation: Hantering av fiberv\u00e4vningseffekten (FWE) och l\u00e4ngdanpassning f\u00f6r PCIe Gen 6"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_74 counter-hierarchy ez-toc-counter ez-toc-custom ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Inneh\u00e5llsf\u00f6rteckning<\/p>\n<span class=\"ez-toc-title-toggle\"><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/#Introduction_to_PCIe_Gen_6_Signal_Integrity_Challenges\" >En introduktion till utmaningarna kring signalintegritet i PCIe Gen 6<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/#Understanding_Skew_in_High-Speed_Differential_Pairs\" >Att f\u00f6rst\u00e5 skevhet i h\u00f6ghastighetsdifferentialpar<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/#In-Pair_Skew_Intra-Pair_Skew\" >Skew inom ett par (Intra-Pair Skew)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/#Factors_Contributing_to_Skew\" >Faktorer som bidrar till skevhet<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/#The_Fiber_Weave_Effect_FWE_Explained\" >Fiber Weave-effekten (FWE) f\u00f6rklarad<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/#The_Microscopic_Dielectric_Imbalance\" >Den mikroskopiska dielektriska obalansen<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/#Mitigation_Strategies_for_FWE\" >Strategier f\u00f6r att mildra effekterna av FWE<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/#Precision_Length_Matching_and_Phase_Compensation\" >Exakt l\u00e4ngdanpassning och faskompensation<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/#Phase_Compensation_at_the_Source\" >Faskompensation vid k\u00e4llan<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/#Corner_and_Bend_Management\" >Hantering av kurvor och sv\u00e4ngar<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-11\" href=\"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/#How_to_Implement_Skew_Compensation_for_PCIe_Gen_6_Step-by-Step_Guide\" >S\u00e5 h\u00e4r implementerar du skevhetskompensation f\u00f6r PCIe Gen 6 (steg-f\u00f6r-steg-guide)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-12\" href=\"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/#Advanced_Considerations_for_64_GTs_Channels\" >Avancerade \u00f6verv\u00e4ganden f\u00f6r kanaler med 64 GT\/s<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-13\" href=\"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/#Via_Stub_Management\" >Via Stub Management<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-14\" href=\"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/#Surface_Roughness_Impact\" >Effekten av ytans oj\u00e4mnhet<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-15\" href=\"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/#Conclusion\" >Slutsats<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-16\" href=\"https:\/\/www.topfastpcb.com\/sv\/blog\/skew-compensation-fwe-pcb\/#Frequently_Asked_Questions_FAQ\" >Ofta st\u00e4llda fr\u00e5gor (FAQ)<\/a><\/li><\/ul><\/nav><\/div>\n<h2><span class=\"ez-toc-section\" id=\"Introduction_to_PCIe_Gen_6_Signal_Integrity_Challenges\"><\/span>En introduktion till utmaningarna kring signalintegritet i PCIe Gen 6<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>\u00d6verg\u00e5ngen till Peripheral Component Interconnect Express (PCIe) generation 6 medf\u00f6r helt nya utmaningar inom konstruktionen av h\u00f6ghastighetskretskort (PCB). PCIe Gen 6, som arbetar med 64 gigatransfer per sekund (GT\/s) och anv\u00e4nder PAM4-signalering (Pulse Amplitude Modulation 4-level), st\u00e4ller h\u00f6ga krav p\u00e5 hantering av signalintegriteten (SI). PAM4 kodar tv\u00e5 bitar per symbol med hj\u00e4lp av fyra sp\u00e4nningsniv\u00e5er, vilket avsev\u00e4rt minskar signal-brusf\u00f6rh\u00e5llandet (SNR) och \u00f6gonh\u00f6jden j\u00e4mf\u00f6rt med den NRZ-signalering (Non-Return-to-Zero) som anv\u00e4ndes i tidigare generationer.<\/p>\n<p>I denna milj\u00f6 med h\u00f6ga frekvenser och sm\u00e5 marginaler kan till och med pikosekunder av fasf\u00f6rskjutning mellan de positiva (P) och negativa (N) sp\u00e5rlinjerna i ett differentialpar leda till att signalens \u00f6gondiagram helt kollapsar. Denna fasf\u00f6rskjutning, som vanligtvis kallas skew, leder till omvandling fr\u00e5n differential- till gemensamt l\u00e4ge, \u00f6kad elektromagnetisk st\u00f6rning (EMI) och f\u00f6r\u00f6dande resonanser i ins\u00e4ttningsf\u00f6rlusten. F\u00f6r att garantera robust l\u00e4nkutbildning och l\u00e5ga bitfelfrekvenser (BER) m\u00e5ste kretskortskonstrukt\u00f6rer implementera rigor\u00f6sa strategier f\u00f6r skevhetskompensation, med s\u00e4rskilt fokus p\u00e5 att mildra Fiber Weave-effekten (FWE) och genomf\u00f6ra noggranna protokoll f\u00f6r l\u00e4ngdanpassning.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Understanding_Skew_in_High-Speed_Differential_Pairs\"><\/span>Att f\u00f6rst\u00e5 skevhet i h\u00f6ghastighetsdifferentialpar<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Skew i differentialpar upptr\u00e4der i tv\u00e5 huvudsakliga former: skew inom samma par och skew mellan olika par. F\u00f6r seriella l\u00e4nkar som PCIe Gen 6, d\u00e4r klock\u00e5terst\u00e4llning \u00e4r integrerad i datastr\u00f6mmen, \u00e4r skew inom samma par den viktigaste parametern att kontrollera.<\/p>\n<div style=\"text-align: center;\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-1.jpg\" alt=\"Skevhetskompensation\" width=\"600\" height=\"400\" class=\"aligncenter size-full wp-image-6417\" srcset=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-1.jpg 600w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-1-300x200.jpg 300w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-1-18x12.jpg 18w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/div>\n<h3><span class=\"ez-toc-section\" id=\"In-Pair_Skew_Intra-Pair_Skew\"><\/span>Skew inom ett par (Intra-Pair Skew)<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p>Skew inom ett par \u00e4r skillnaden i utbredningsf\u00f6rdr\u00f6jning mellan den icke-inverterande och den inverterande ledningen i ett enskilt differentialpar. Idealt sett b\u00f6r signaler som s\u00e4nds ut samtidigt anl\u00e4nda till mottagaren exakt samtidigt och vara 180 grader fasf\u00f6rskjutna. N\u00e4r skew uppst\u00e5r utj\u00e4mnar sig signalerna inte l\u00e4ngre perfekt. Denna felinriktning leder till att en del av den differentiella signalen omvandlas till en gemensammodsignal. Gemensammodsignaler \u00e4r mycket o\u00f6nskade eftersom de inte drar nytta av den differentiella signaleringens brusimmunitet, \u00f6kar EMI-utsl\u00e4ppen och skapar resonansdalar i profilen f\u00f6r differentiell ins\u00e4ttningsf\u00f6rlust (SDD21). F\u00f6r PCIe Gen 6 ligger den totala till\u00e5tna skevhetsmarginalen per par \u00f6ver hela kanalen vanligtvis i storleksordningen n\u00e5gra pikosekunder.<\/p>\n<h3><span class=\"ez-toc-section\" id=\"Factors_Contributing_to_Skew\"><\/span>Faktorer som bidrar till skevhet<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p>Flera faktorer bidrar till skevhet mellan ledningspar vid PCB-ledningsdragning:<br \/>&#8211; <strong>Asymmetrisk routning:<\/strong> Oj\u00e4mna ledningsl\u00e4ngder p\u00e5 grund av okompenserade b\u00f6jar, genomg\u00e5ngsh\u00e5l eller komponentanslutningar.<br \/>&#8211; <strong>Variationer i glasv\u00e4v:<\/strong> De mikroskopiska oj\u00e4mnheterna i kretskortets substratmaterial.<br \/>&#8211; <strong>Kopparns ytr\u00e5het:<\/strong> Variationer i kopparsp\u00e5rets fysiska profil, \u00e4ven om detta vanligtvis \u00e4r en sekund\u00e4r faktor f\u00f6r fasen.<br \/>&#8211; <strong>Avbrott i anslutningar och kapslingar:<\/strong> Anslutningskonfigurationer som i sig medf\u00f6r skillnader i l\u00e4ngd.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"The_Fiber_Weave_Effect_FWE_Explained\"><\/span>Fiber Weave-effekten (FWE) f\u00f6rklarad<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Vid tillverkning av h\u00f6ghastighetskretskort best\u00e5r det dielektriska materialet vanligtvis av en f\u00f6rst\u00e4rkningsmatris av glasfiber som \u00e4r impregnerad med epoxiharts (till exempel FR4, Megtron eller Rogers-material). Glasfibern ger strukturell styvhet, medan hartset fungerar som bindemedel. Dessa tv\u00e5 material har dock v\u00e4sentligt olika dielektricitetskonstanter (Dk). Glasfibrerna har i allm\u00e4nhet en h\u00f6gre Dk (cirka 6,0) j\u00e4mf\u00f6rt med det omgivande hartset (cirka 3,0).<\/p>\n<h3><span class=\"ez-toc-section\" id=\"The_Microscopic_Dielectric_Imbalance\"><\/span>Den mikroskopiska dielektriska obalansen<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p>N\u00e4r differentialpar dras \u00f6ver detta heterogena substrat blir den fysiska inriktningen av ledningsbanorna i f\u00f6rh\u00e5llande till glasv\u00e4vnaden en avg\u00f6rande faktor. Om den positiva ledningen i ett differentialpar dras direkt \u00f6ver en t\u00e4t glasbunt medan den negativa ledningen dras \u00f6ver ett hartsrikt mellanrum (\u201df\u00f6nstret\u201d), kommer de tv\u00e5 signalerna att uts\u00e4ttas f\u00f6r olika effektiva dielektricitetskonstanter.<\/p>\n<div style=\"text-align: center;\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-2.jpg\" alt=\"Skevhetskompensation\" width=\"600\" height=\"400\" class=\"aligncenter size-full wp-image-6418\" srcset=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-2.jpg 600w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-2-300x200.jpg 300w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-2-18x12.jpg 18w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/div>\n<p>Eftersom utbredningshastigheten f\u00f6r en elektromagnetisk signal \u00e4r omv\u00e4nt proportionell mot kvadratroten av den dielektriska konstanten, kommer signalen som f\u00e4rdas genom glasbuntarna med h\u00f6gre Dk att sprida sig l\u00e5ngsammare \u00e4n signalen som f\u00e4rdas genom h\u00e5lrummet med harts med l\u00e4gre Dk. Denna skillnad i hastighet ger upphov till en f\u00f6rdr\u00f6jning i utbredningen, vilket genererar en skevhet inom paret som \u00e4r helt oberoende av den fysiska ledningsl\u00e4ngden. Detta fenomen kallas Fiber Weave Effect (FWE).<\/p>\n<p>Vid Nyquist-frekvenser p\u00e5 32 GHz f\u00f6r PCIe Gen 6 kan \u00e4ven en liten FWE-orsakad skevhet ta slut p\u00e5 hela felbudgeten. Standardglasv\u00e4vningar som 106 eller 1080 har tydliga mellanrum mellan buntarna, vilket g\u00f6r dem mycket k\u00e4nsliga f\u00f6r FWE.<\/p>\n<h3><span class=\"ez-toc-section\" id=\"Mitigation_Strategies_for_FWE\"><\/span>Strategier f\u00f6r att mildra effekterna av FWE<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p>F\u00f6r att hantera FWE i PCIe Gen 6-konstruktioner m\u00e5ste kretskortskonstrukt\u00f6rer anv\u00e4nda en eller flera av f\u00f6ljande tekniker: <strong>L\u00e4r dig mer om <a href=\"\/sv\/blog\/bga-underfill-pcba\/\">BGA-underfyllning: F\u00f6rb\u00e4ttrad tillf\u00f6rlitlighet hos kretskort mot mekaniska st\u00f6tar och termisk belastning<\/a>.<\/strong><\/p>\n<ul>\n<li><strong>Mekaniskt spridat glas:<\/strong> Genom att anv\u00e4nda avancerade laminat med mekaniskt utspridda eller utplattade glasfibrer (t.ex. v\u00e4vningarna 1078, 1086, 2116 och 3313). Dessa v\u00e4vningar minimerar hartsfickorna och ger ledningarna en mer homogen Dk-profil.<\/li>\n<li><strong>Diagonal ledningsdragning:<\/strong> Att dra h\u00f6ghastighetsledningar i en vinkel (vanligtvis 10 till 15 grader) i f\u00f6rh\u00e5llande till kretskortets prim\u00e4ra X-Y-axel. Detta s\u00e4kerst\u00e4ller att b\u00e5da ledningarna korsar alternerande glasfiberbuntar och hartsmellanrum i lika stor utstr\u00e4ckning, vilket utj\u00e4mnar Dk-variationerna \u00f6ver ledningens hela l\u00e4ngd.<\/li>\n<li><strong>Zickzack-ruttplanering:<\/strong> Om diagonal dragning inte \u00e4r m\u00f6jlig p\u00e5 grund av kretskortets form eller begr\u00e4nsningar i komponentt\u00e4theten, kan man uppn\u00e5 en liknande utj\u00e4mningseffekt genom att dra ledningarna i ett subtilt sicksackm\u00f6nster.<\/li>\n<li><strong>Roterat konstverk:<\/strong> Kretskortstillverkaren kan under tillverkningen rotera hela panelens m\u00f6nster en viss vinkel i f\u00f6rh\u00e5llande till laminatarket, vilket p\u00e5 ett effektivt s\u00e4tt simulerar diagonal fr\u00e4sning f\u00f6r ortogonala ledare.<\/li>\n<\/ul>\n<h2><span class=\"ez-toc-section\" id=\"Precision_Length_Matching_and_Phase_Compensation\"><\/span>Exakt l\u00e4ngdanpassning och faskompensation<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>\u00c4ven om FWE-d\u00e4mpning stabiliserar \u00f6verf\u00f6ringshastigheten m\u00e5ste de fysiska ledningsl\u00e4ngderna fortfarande noggrant anpassas f\u00f6r att eliminera geometrisk skevhet. F\u00f6r PCIe Gen 6 r\u00e4cker det inte med en enkel l\u00e4ngdanpassning; en verklig faskompensation m\u00e5ste uppn\u00e5s.<\/p>\n<h3><span class=\"ez-toc-section\" id=\"Phase_Compensation_at_the_Source\"><\/span>Faskompensation vid k\u00e4llan<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p>En grundl\u00e4ggande regel f\u00f6r h\u00f6ghastighetsledningsdragning \u00e4r att l\u00e4ngdskillnader m\u00e5ste kompenseras exakt d\u00e4r de uppst\u00e5r. Om en l\u00e4ngdskillnad uppst\u00e5r vid en BGA-anslutning eller en kontaktstift m\u00e5ste kompensationsslingan (eller \u201dtrombon\u201d- respektive \u201ddragspelsstrukturen\u201d) placeras omedelbart intill denna diskontinuitet.<\/p>\n<p>Om en l\u00e4ngdskillnad till\u00e5ts sprida sig l\u00e4ngs kanalen innan den korrigeras, kommer omvandlingen fr\u00e5n differentiell till gemensam mod redan att ha \u00e4gt rum. Signalen i gemensam mod kommer att f\u00e4rdas med en n\u00e5got annorlunda hastighet \u00e4n den differentiella signalen p\u00e5 grund av modaldispersionsegenskaperna hos mikrostrips och striplines. Kompensering vid den bortre \u00e4nden kan visserligen korrigera DC-l\u00e4ngden, men den kommer inte att kunna \u00e5terst\u00e4lla AC-fasen \u00f6ver hela frekvensbandet. <strong>L\u00e4r dig mer om <a href=\"\/sv\/blog\/extreme-thermal-cycling-aerospace-pcb\/\">Extrema temperaturv\u00e4xlingar: Tillf\u00f6rlitlighetstestning och materialval f\u00f6r kretskort inom flyg- och rymdindustrin<\/a>.<\/strong><\/p>\n<h3><span class=\"ez-toc-section\" id=\"Corner_and_Bend_Management\"><\/span>Hantering av kurvor och sv\u00e4ngar<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p>N\u00e4r ett differentialpar passerar en kurva tillryggal\u00e4gger den yttre ledningen naturligtvis en l\u00e4ngre str\u00e4cka \u00e4n den inre. F\u00f6r PCIe Gen 6 m\u00e5ste dessa b\u00f6jar hanteras noggrant. Konstrukt\u00f6rer av h\u00f6ghastighetskretsar anv\u00e4nder vanligtvis okopplade bump eller specialiserade fasanpassande geometrier direkt efter en b\u00f6j f\u00f6r att utj\u00e4mna den elektriska l\u00e4ngden. Alternativt kan man minimera diskontinuiteten i differentialimpedansen och uppkomsten av lokal skevhet genom att anv\u00e4nda t\u00e4t koppling och mjuka b\u00e5gar ist\u00e4llet f\u00f6r skarpa 45-gradersvinklar.<\/p>\n<h2><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation.jpg\" alt=\"Skevhetskompensation\" width=\"600\" height=\"400\" class=\"aligncenter size-full wp-image-6416\" srcset=\"https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation.jpg 600w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-300x200.jpg 300w, https:\/\/www.topfastpcb.com\/wp-content\/uploads\/2026\/08\/Skew-Compensation-18x12.jpg 18w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/h2>\n<h2><span class=\"ez-toc-section\" id=\"How_to_Implement_Skew_Compensation_for_PCIe_Gen_6_Step-by-Step_Guide\"><\/span>S\u00e5 h\u00e4r implementerar du skevhetskompensation f\u00f6r PCIe Gen 6 (steg-f\u00f6r-steg-guide)<span class=\"ez-toc-section-end\"><\/span><\/h2><div class=\"schema-how-to wp-block-yoast-how-to-block\"><p class=\"schema-how-to-description\">F\u00f6lj dessa tekniska riktlinjer.<\/p> <ol class=\"schema-how-to-steps\"><li class=\"schema-how-to-step\" id=\"how-to-step-1\"><strong class=\"schema-how-to-step-name\">V\u00e4lj l\u00e4mpligt dielektriskt material och glasv\u00e4v<\/strong> <p class=\"schema-how-to-step-text\">B\u00f6rja med att r\u00e5dg\u00f6ra med din kretskortstillverkare och laminatleverant\u00f6r. Specificera material med extremt l\u00e5ga f\u00f6rluster och en platt eller mekaniskt utspridd glasv\u00e4vstruktur (till exempel 2116 eller 3313). Se till att materialets Dk- och Df-egenskaper \u00e4r stabila \u00f6ver hela frekvensspektrumet upp till minst 40 GHz.<\/p> <\/li><li class=\"schema-how-to-step\" id=\"how-to-step-2\"><strong class=\"schema-how-to-step-name\">Fastst\u00e4ll routingstrategin f\u00f6r att begr\u00e4nsa FWE<\/strong> <p class=\"schema-how-to-step-text\">Best\u00e4m hur FWE ska hanteras utifr\u00e5n kretskortets formfaktor och tillverkningsbegr\u00e4nsningar. Om layouten till\u00e5ter det, fastst\u00e4ll en global designregel f\u00f6r att dra alla PCIe Gen 6-differentialpar i en vinkel p\u00e5 10 till 15 grader i f\u00f6rh\u00e5llande till de ortogonala axlarna. Om s\u00e5 inte \u00e4r fallet, kr\u00e4v zickzack-dragning eller f\u00f6rhandla med tillverkaren om en rotation av kretskortet.<\/p> <\/li><li class=\"schema-how-to-step\" id=\"how-to-step-3\"><strong class=\"schema-how-to-step-name\">Fastst\u00e4lla strikta regler f\u00f6r l\u00e4ngdmatchning inom par<\/strong> <p class=\"schema-how-to-step-text\">Konfigurera begr\u00e4nsningshanteraren i ditt EDA-verktyg s\u00e5 att den till\u00e4mpar strikta regler f\u00f6r l\u00e4ngdanpassning inom par. Vid drift med 64 GT\/s b\u00f6r den dynamiska fasavvikelsen inom paret begr\u00e4nsas till mindre \u00e4n 1 pikosekund (vilket motsvarar ungef\u00e4r 5\u20136 mil, beroende p\u00e5 Dk). St\u00e4ll in dynamisk faskontroll ist\u00e4llet f\u00f6r statisk l\u00e4ngdkontroll f\u00f6r att s\u00e4kerst\u00e4lla kontinuerlig inriktning.<\/p> <\/li><li class=\"schema-how-to-step\" id=\"how-to-step-4\"><strong class=\"schema-how-to-step-name\">Utf\u00f6r lokaliserad faskompensation<\/strong> <p class=\"schema-how-to-step-text\">Dra differentialparen noggrant och se till att eventuella geometriska avvikelser som orsakas av komponentanslutningar, via-\u00f6verg\u00e5ngar eller b\u00f6jar korrigeras omedelbart. Anv\u00e4nd t\u00e4ta, lokala slingor. Undvik stora, svepande kompensationsstrukturer som kan orsaka o\u00f6nskad kapacitiv eller induktiv koppling.<\/p> <\/li><li class=\"schema-how-to-step\" id=\"how-to-step-5\"><strong class=\"schema-how-to-step-name\">Validering genom elektromagnetisk 3D-simulering<\/strong> <p class=\"schema-how-to-step-text\">Innan layouten slutf\u00f6rs ska de kritiska PCIe Gen 6-kanalerna extraheras med hj\u00e4lp av en 3D-l\u00f6sare f\u00f6r elektromagnetisk (EM) fullv\u00e5gsanalys. Analysera S-parametrarna i blandat l\u00e4ge, med s\u00e4rskilt fokus p\u00e5 den differentiella ins\u00e4ttningsf\u00f6rlusten (SDD21) och omvandlingen fr\u00e5n differentiellt till gemensamt l\u00e4ge (SCD21). Leta efter skarpa resonansdalar i SDD21-profilen, vilket ofta indikerar okompenserad fasf\u00f6rskjutning. Justera layouten utifr\u00e5n simuleringsresultaten tills kanalen uppfyller PCIe Gen 6-kompatibilitetskraven.<\/p> <\/li><\/ol><\/div><p>F\u00f6r att implementera en robust strategi f\u00f6r skevhetskompensation kr\u00e4vs ett systematiskt tillv\u00e4gag\u00e5ngss\u00e4tt, fr\u00e5n schematisk utformning till fysisk layout och simulering. F\u00f6lj dessa steg f\u00f6r att s\u00e4kerst\u00e4lla att PCIe Gen 6-specifikationerna uppfylls.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Advanced_Considerations_for_64_GTs_Channels\"><\/span>Avancerade \u00f6verv\u00e4ganden f\u00f6r kanaler med 64 GT\/s<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>I takt med att datahastigheterna forts\u00e4tter att \u00f6ka blir definitionen av \u201dledningsl\u00e4ngd\u201d allt mer komplex. Verktyg f\u00f6r kretskortskonstruktion m\u00e5ste \u00e4ven ta h\u00e4nsyn till \u00f6verg\u00e5ngarna l\u00e4ngs Z-axeln. L\u00e4ngden p\u00e5 genomg\u00e5ngsh\u00e5l, s\u00e4rskilt avst\u00e5ndet fr\u00e5n det \u00f6versta lagret till de inre signallagren, medf\u00f6r lokala f\u00f6rdr\u00f6jningar som m\u00e5ste kompenseras symmetriskt.<\/p>\n<h3><span class=\"ez-toc-section\" id=\"Via_Stub_Management\"><\/span>Via Stub Management<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p>F\u00f6r PCIe Gen 6 fungerar via-stubbar som resonansantenner och m\u00e5ste kontrolleras noggrant. Backdrilling (borrning med kontrollerat djup) eller anv\u00e4ndning av blinda\/begravda viaer \u00e4r obligatoriskt f\u00f6r att eliminera resonansstubbar som kan skapa djupa nollpunkter i kanalens ins\u00e4ttningsf\u00f6rlustprofil. Vid kompensation f\u00f6r skevhet n\u00e4ra viaer m\u00e5ste man se till att kompensationsstrukturen tar h\u00e4nsyn till den elektriska l\u00e4ngden p\u00e5 sj\u00e4lva via-cylindern. <strong>L\u00e4r dig mer om <a href=\"\/sv\/blog\/embedded-pcb-components-iot\/\">Inbyggda komponenter: Miniatyrisering av IoT-enheter med inbyggda kretskortskomponenter<\/a>.<\/strong><\/p>\n<h3><span class=\"ez-toc-section\" id=\"Surface_Roughness_Impact\"><\/span>Effekten av ytans oj\u00e4mnhet<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p>Medan FWE styr fasvariationen har kopparytans oj\u00e4mnhet en avg\u00f6rande inverkan p\u00e5 ins\u00e4ttningsf\u00f6rlusten vid Nyquist-frekvenser p\u00e5 32 GHz. Den s\u00e5 kallade \u201dskineffekten\u201d tvingar h\u00f6gfrekventa str\u00f6mmar att f\u00e4rdas l\u00e4ngs kopparsp\u00e5rets yttre yta. Grovare kopparbehandlingar (som standard-RTF) \u00f6kar den effektiva str\u00e4ckl\u00e4ngden, vilket orsakar \u00f6verdriven d\u00e4mpning och fasdispersion. Ange kopparfolier med l\u00e5g profil (LP), mycket l\u00e5g profil (VLP) eller extremt l\u00e5g profil (HVLP) f\u00f6r att bevara signalintegriteten och minimera of\u00f6ruts\u00e4gbara fasf\u00f6rskjutningar orsakade av variationer i ytornas grovhet.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Conclusion\"><\/span>Slutsats<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Att utforma kretskort f\u00f6r PCIe Gen 6 kr\u00e4ver ett paradigmskifte i hur ingenj\u00f6rer hanterar signalintegritet. Den enorma hastigheten p\u00e5 64 GT\/s vid PAM4-signalering minskar drastiskt toleransen f\u00f6r eventuella brister i kanalerna. Att hantera skevhet inom par handlar inte l\u00e4ngre bara om att anpassa ledningsl\u00e4ngderna p\u00e5 ett 2D-plan; det kr\u00e4ver ett helhetsperspektiv som beaktar anslutningarnas 3D-geometri, de dielektriska materialens mikroskopiska struktur och det dynamiska beteendet hos elektromagnetiska v\u00e5gor. Genom att noggrant hantera Fiber Weave-effekten, implementera lokaliserad faskompensation och utnyttja avancerad EM-simulering kan ingenj\u00f6rer framg\u00e5ngsrikt implementera robusta och tillf\u00f6rlitliga PCIe Gen 6-arkitekturer. <strong>L\u00e4r dig mer om <a href=\"\/sv\/blog\/return-path-optimization-si\/\">Optimering av returv\u00e4gen: Utformning av stabila referensplan f\u00f6r signalintegritet vid h\u00f6ga frekvenser<\/a>.<\/strong><\/p>\n<h2><span class=\"ez-toc-section\" id=\"Frequently_Asked_Questions_FAQ\"><\/span>Ofta st\u00e4llda fr\u00e5gor (FAQ)<span class=\"ez-toc-section-end\"><\/span><\/h2><div class=\"schema-faq wp-block-yoast-faq-block\"><div class=\"schema-faq-section\" id=\"faq-question-1\"><strong class=\"schema-faq-question\">Vad \u00e4r den h\u00f6gsta till\u00e5tna skevheten mellan paren f\u00f6r ett differentiellt par i PCIe Gen 6?<\/strong> <p class=\"schema-faq-answer\">\u00c4ven om den exakta budgeten beror p\u00e5 kanalens sammans\u00e4ttning (kretspaket, kontaktdon, kablar), \u00e4r den vanliga tumregeln f\u00f6r kretskortdelen av en PCIe Gen 6-l\u00e4nk att h\u00e5lla skevheten inom ett par under 1 till 2 pikosekunder (motsvarande cirka 5 till 10 mil i ledningsl\u00e4ngd, beroende p\u00e5 material). \u00c4ven denna lilla avvikelse kan f\u00f6rs\u00e4mra PAM4-\u00f6gondiagrammet avsev\u00e4rt.<\/p> <\/div> <div class=\"schema-faq-section\" id=\"faq-question-2\"><strong class=\"schema-faq-question\">Varf\u00f6r kan jag inte bara kompensera f\u00f6r l\u00e4ngdskillnaden p\u00e5 mottagarsidan?<\/strong> <p class=\"schema-faq-answer\">Om en skevhet uppst\u00e5r tidigt i kanalen (t.ex. vid utg\u00e5ngen fr\u00e5n s\u00e4ndarenheten) skapas en signalkomponent i gemensamt l\u00e4ge. Eftersom differential- och gemensamt-l\u00e4gessignaler fortplantar sig med n\u00e5got olika hastigheter i standardkorssnitt p\u00e5 kretskort, f\u00f6rskjuts fasf\u00f6rh\u00e5llandet n\u00e4r signalen f\u00e4rdas. Kompensering vid den bortre \u00e4nden kan visserligen matcha den fysiska l\u00e4ngden, men lyckas inte \u00e5terst\u00e4lla differentialfasen korrekt \u00f6ver alla frekvenser, vilket leder till signalf\u00f6rs\u00e4mring.<\/p> <\/div> <div class=\"schema-faq-section\" id=\"faq-question-3\"><strong class=\"schema-faq-question\">\u00c4r sicksack- eller diagonalruttning b\u00e4ttre f\u00f6r att minska fiberv\u00e4vningseffekten?<\/strong> <p class=\"schema-faq-answer\">Diagonal ledningsdragning (ledningsdragning utanf\u00f6r axeln) anses i allm\u00e4nhet vara \u00f6verl\u00e4gsen och ge ett mer j\u00e4mnt resultat n\u00e4r det g\u00e4ller att minska FWE. Sicksack-ledningsdragning kan ibland orsaka mindre impedansavbrott vid v\u00e4ndpunkterna, s\u00e4rskilt om sicksack-segmenten \u00e4r korta i f\u00f6rh\u00e5llande till signalens v\u00e5gl\u00e4ngd. Om utrymmet p\u00e5 kretskortet eller dess form emellertid f\u00f6rhindrar diagonal dragning eller rotation av panelen, \u00e4r sicksackdragning ett fullgott alternativ n\u00e4r den simuleras p\u00e5 r\u00e4tt s\u00e4tt.<\/p> <\/div> <div class=\"schema-faq-section\" id=\"faq-question-4\"><strong class=\"schema-faq-question\">Beh\u00f6ver jag oroa mig f\u00f6r skevhet mellan par i PCIe Gen 6?<\/strong> <p class=\"schema-faq-answer\">PCIe-arkitekturen hanterar i sig skevhet mellan par (skevhet mellan banor) p\u00e5 protokoll- och kretsniv\u00e5 genom en process som kallas \u201dlane deskewing\u201d under l\u00e4nkutbildningen. D\u00e4rf\u00f6r har kretskortskonstrukt\u00f6rer betydligt st\u00f6rre toleranser f\u00f6r l\u00e4ngdanpassning mellan par (ofta upp till flera tum) j\u00e4mf\u00f6rt med de extremt sn\u00e4va begr\u00e4nsningarna som kr\u00e4vs f\u00f6r skevhet inom ett par.<\/p> <\/div> <div class=\"schema-faq-section\" id=\"faq-question-5\"><strong class=\"schema-faq-question\">P\u00e5 vilket s\u00e4tt g\u00f6r PAM4-signalering att kompensering av skevhet blir viktigare \u00e4n i tidigare generationer av PCIe?<\/strong> <p class=\"schema-faq-answer\">PAM4 anv\u00e4nder fyra sp\u00e4nningsniv\u00e5er f\u00f6r att \u00f6verf\u00f6ra tv\u00e5 bitar per symbol, vilket minskar den vertikala \u00f6gonh\u00f6jden (signal-brusf\u00f6rh\u00e5llandet) med ungef\u00e4r en faktor tre j\u00e4mf\u00f6rt med NRZ-signalering som anv\u00e4nds i PCIe Gen 5 och tidigare versioner. Med betydligt mindre marginal f\u00f6r brus och jitter f\u00e5r varje f\u00f6rvr\u00e4ngning som orsakas av fasf\u00f6rskjutning en oproportionerligt stor inverkan p\u00e5 bitfelfrekvensen (BER) i ett PAM4-system.<\/p> <\/div> <\/div>","protected":false},"excerpt":{"rendered":"<p>Introduction to PCIe Gen 6 Signal Integrity Challenges The transition to Peripheral Component Interconnect Express (PCIe) Generation 6 introduces unprecedented challenges in high-speed printed circuit board (PCB) design. Operating at 64 GigaTransfers per second (GT\/s) and utilizing Pulse Amplitude Modulation 4-level (PAM4) signaling, PCIe Gen 6 demands stringent signal integrity (SI) management. PAM4 encodes two [&hellip;]<\/p>","protected":false},"author":1,"featured_media":6419,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_yoast_wpseo_focuskw":"Skew Compensation","_yoast_wpseo_title":"Skew Compensation: Managing Fiber Weave Effect (FWE) and Length Matching for PCIe Gen 6","_yoast_wpseo_metadesc":"Explore advanced techniques for managing Fiber Weave Effect (FWE) and achieving precise length matching in PCIe Gen 6 PCB designs to meet strict skew compensation requirements.","footnotes":""},"categories":[108],"tags":[580,582,581,110,579,578],"class_list":["post-6244","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news","tag-fiber-weave-effect","tag-high-speed-design","tag-length-matching","tag-pcb-design","tag-pcie-gen-6","tag-skew-compensation"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v25.1 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ 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