Common Issues in Improving PCB Reliability

How to Calculate PCB Impedance?

Calculating PCB impedance ensures signal integrity, especially for high-speed and RF circuits.

1. Determine PCB Stackup & Geometry

• Layer count: Single, double, or multilayer.
• Trace width (W) and thickness (T): Critical for impedance control.
• Dielectric thickness (H): Distance between signal layer and reference plane (e.g., ground).
• Copper weight: Typically 0.5 oz (17.5 µm) to 2 oz (70 µm).

2. Identify Dielectric Constant (Dk or εᵣ)

• FR-4: ~4.3–4.8 (varies with frequency).
• Rogers RO4003C: ~3.38 (low-loss for RF).
• Polyimide: ~3.5 (flexible PCBs).
• Note: Dk decreases slightly at higher frequencies.

3. Choose Impedance Calculation Method

Microstrip (outer layer trace over ground plane):

Stripline (inner layer between two ground planes):

Differential Pair: Requires spacing (S) between traces.

4. Use Impedance Calculators or Tools

• Online Tools: Saturn PCB Toolkit, EEWeb Calculator.
• PCB Software: Altium Designer, KiCad, or Cadence include built-in impedance calculators.
• EM Simulators: Ansys HFSS, CST (for advanced designs).

5. Optimize Design Based on Results

• Adjust trace width (↑ width → ↓ impedance).
• Modify dielectric thickness (↑ H → ↑ impedance).
• Tweak trace spacing for differential pairs.
• Select materials with appropriate Dk (e.g., Rogers for RF).

Example Calculation (FR-4 Microstrip)
Given:

• Trace width (W) = 0.2 mm
• Dielectric thickness (H) = 0.15 mm
• Copper thickness (T) = 0.035 mm
• εᵣ = 4.5

Using the microstrip formula:

Matches standard 50Ω impedance for RF signals.

How to consider signal integrity in PCB design?

1. Layout Design

In PCB layout design, it is important to consider the layout of signal lines, power lines, and ground lines, and to avoid interference caused by the crossing of signal lines, power lines, and ground lines. Additionally, it is essential to minimize the length of signal lines to reduce crosstalk and delay.

2. Impedance Matching

When designing high-speed signal lines, impedance matching must be performed to ensure that the impedance of the signal lines matches the impedance of the signal source and load, thereby avoiding signal reflection and crosstalk.

3. Signal Line Routing

In PCB design, the routing of signal lines also affects signal integrity and must follow certain rules. For example, differential signal lines should maintain a certain spacing and be routed in parallel, while single-ended signal lines should be routed parallel to ground lines, and signal line bends should be minimized.

4. Power and Grounding

In PCB design, the design of power and grounding also affects signal integrity. Stable power and grounding should be used, and the resistance and inductance of power and grounding should be minimized as much as possible.

5. Simulation Verification

After the PCB design is completed, simulation verification is required to ensure that signal integrity meets the requirements. Through simulation, issues such as signal delay, reflection, and crosstalk can be detected, and the PCB design can be optimized.

How to Consider Electromagnetic Compatibility (EMC) in PCB Design?

1. PCB Layout for EMC

• Minimize Parallel Routing: Avoid long parallel runs between signal and power/ground traces to reduce crosstalk and electromagnetic coupling.
• Critical Signal Isolation: Separate high-speed (e.g., clocks, RF) and sensitive analog signals from noisy circuits (e.g., switching power supplies).
• Layer Stackup Strategy:
• Use solid ground planes adjacent to signal layers to provide shielding.
• Route high-speed signals on inner layers between ground planes for containment.

2. Grounding Techniques

• Low-Impedance Ground Planes: Use unbroken ground planes to minimize ground loops and reduce radiated emissions.
• Split Grounds Carefully: Separate analog/digital grounds only when necessary, with a single connection point (e.g., ferrite bead or 0Ω resistor).
• Via Stitching: Place multiple ground vias around high-frequency traces or board edges to suppress cavity resonances.

3. Filtering & Suppression

• Ferrite Beads: Add to power/IO lines to block high-frequency noise.
• Decoupling Capacitors: Place near IC power pins (e.g., 0.1μF + 1μF) to filter high- and mid-frequency noise.
• Common-Mode Chokes: Use on differential pairs (e.g., USB, Ethernet) to suppress common-mode radiation.

4. Shielding & Interface Design

• Cable Shielding: Use shielded connectors (e.g., USB, HDMI) with 360° grounding to the chassis.
• Board-Level Shielding: Add metal cans or conductive coatings over sensitive RF circuits.
• Edge Protection: Route sensitive traces away from board edges; use guard traces or grounded copper pour around them.

5. Simulation & Testing

• Pre-Layout Analysis: Use tools like ANSYS HFSS or CST to model radiation hotspots.
• Post-Layout Verification:
• Conduct near-field scans to identify emission sources.
• Perform compliance testing (e.g., FCC, CE) for radiated/conducted emissions.
• Design Iteration: Optimize based on test results (e.g., adding termination resistors or adjusting trace spacing).

Example Fixes:

• A 100MHz clock radiating excessively: Add series termination resistors or route between ground planes.
• Switching power supply noise: Implement π-filters (LC) at the input/output.

By integrating these practices, PCBs can meet EMC standards (e.g., IEC 61000) while minimizing costly redesigns. Always prototype and test early!

How to Consider Power Integrity (PI) in PCB Design?

1. Power Trace Layout

• Short and Wide Traces: Minimize resistance (R) and parasitic inductance (L) to reduce voltage drop and noise.
• Avoid Parallel Routing with Signal Traces: Prevent power noise from coupling into sensitive signals (e.g., clocks, analog circuits).
• Layer Strategy:
• In multilayer boards, dedicate entire layers to power and ground planes.
• Critical power rails (e.g., CPU core voltage) should have dedicated power planes.

2. Power Filtering

• Decoupling Capacitors:
• Bulk electrolytic capacitors (10–100μF) at power inputs to stabilize voltage.
• Small ceramic capacitors (0.1μF) near IC pins to filter high-frequency noise.
• LC Filters:
• Add π-filters (capacitor + inductor) for noise-sensitive modules (e.g., PLLs).

3. Power and Grounding

• Low-Impedance Return Paths:
• Use solid ground planes; avoid splits that cause impedance discontinuities.
• Multiple vias to connect power/ground planes (reduces via inductance).
• Star Grounding:
• Separate high-power and sensitive circuits, with single-point grounding.

4. Simulation and Validation

• PDN (Power Delivery Network) Analysis:
• Target impedance: ( Z_{\text{target}} = \frac{\Delta V}{\Delta I} ).
• Tools: ANSYS SIwave, Cadence Sigrity.
• Ripple and Noise Testing:
• Verify power noise levels with oscilloscopes or simulations.

How to Incorporate Design for Testability (DFT) in PCB Design?

1. Test Points and Interfaces

• Critical Signal Test Points:
• Provide vias or pads (diameter ≥1mm, spacing ≥2.54mm) for probe access.
• Label test points (e.g., TP1, TP2).
• Standard Interfaces:
• Place JTAG, UART, or SWD interfaces near board edges.

2. Board Labeling (Silkscreen)

• Component Markings:
• Label reference designators (e.g., R1, C2), polarity (+/-), and Pin 1.
• Use high-contrast silkscreen (white/black).
• Functional Zones:
• Outline areas (e.g., “Power Section”) for easy identification.

3. Programmable Test Techniques

• Boundary Scan (JTAG):
• IEEE 1149.1-compliant ICs (e.g., FPGAs, MCUs) enable interconnect testing.
• Automated Test Equipment (ATE):
• Reserve test fixture interfaces (e.g., pogo pin pads).

4. Simulation and Validation

• DFT Rule Checks:
• Ensure test point coverage (e.g., >90% of nets accessible).
• Fault Mode Analysis:
• Validate test circuits via SPICE simulations.

Key Design Principles Comparison

Examples:

• PI Optimization: DDR4 memory power planes with multiple 0805 0.1μF caps (target impedance ≤0.1Ω).
• DFT Implementation: Industrial control board with 20 test points for automated flying probe testing.

By systematically addressing PI and DFT, designers can enhance power performance, test efficiency, and production reliability.